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dc.contributor.authorLin, CCen_US
dc.contributor.authorShih, YHen_US
dc.contributor.authorChang, HCen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:18:54Z-
dc.date.available2014-12-08T15:18:54Z-
dc.date.issued2005-06-01en_US
dc.identifier.issn1057-7122en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2005.849106en_US
dc.identifier.urihttp://hdl.handle.net/11536/13606-
dc.description.abstractIn this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-mu m standard CMOS process. The test results show that 30 similar to 40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.en_US
dc.language.isoen_USen_US
dc.subjectadd-compare-selecten_US
dc.subjectpath mergingen_US
dc.subjectpath predictionen_US
dc.subjectsurvivor memoryen_US
dc.subjectViterbi decoderen_US
dc.titleDesign of a power-reduction viterbi decoder for WLAN applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2005.849106en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume52en_US
dc.citation.issue6en_US
dc.citation.spage1148en_US
dc.citation.epage1156en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000229818800012-
dc.citation.woscount27-
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