標題: Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
作者: Chen, Chien-Ju
Chen, Yin-Nien
Fan, Ming-Long
Hu, Vita Pi-Ho
Su, Pin
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2014
摘要: In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on ION and IOFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.
URI: http://hdl.handle.net/11536/136139
ISBN: 978-1-4799-7439-9
期刊: 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
顯示於類別:會議論文