完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Syu, Jin-Siang | en_US |
dc.contributor.author | Meng, Chinchun | en_US |
dc.contributor.author | Teng, Ya-Hui | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:18:58Z | - |
dc.date.available | 2014-12-08T15:18:58Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2801-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13623 | - |
dc.description.abstract | An X-band Weaver-Hartley dual-conversion low-IF downconverter is demonstrated in this paper using 0.35-mu m SiGe heterojunction bipolar transistor (HUT) technology. The first image signal is shifted away from the IF band due to the complex Weaver architecture while the second image signal is eliminated by a polyphase filter in the following Hartley architecture. In this work, a resonant LC load is employed at the first-stage mixer to improve both gain and linearity. As a result, the demonstrated downconverter achieves a conversion gain of 8 dB, single-sideband noise figure of 18 dB, IP(1dB) of -9 dBm, and IIP(3) of 0 dBm, respectively, while consuming 75 mW at a 3.3-V supply. Moreover, the first and second image-rejection ratios are better than 43 and 40 dB when IF frequency ranges from 15 to 100 MHz. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Weaver architecture | en_US |
dc.subject | Hartley architecture | en_US |
dc.subject | dual conversion | en_US |
dc.subject | image rejection | en_US |
dc.title | X-Band Weaver-Hartley Low-IF Downconverter With a Resonant LC Load | en_US |
dc.type | Article | en_US |
dc.identifier.journal | APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 | en_US |
dc.citation.spage | 1168 | en_US |
dc.citation.epage | 1171 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000279924300296 | - |
顯示於類別: | 會議論文 |