標題: | A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end |
作者: | Chen, WZ Cheng, YL Lin, DS 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | limiting amplifier;optical receiver;three-dimensional symmetric transformer;transimpedance amplifier |
公開日期: | 1-六月-2005 |
摘要: | A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-mu m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV((pp)). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB Omega and -3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12 dBm at a bit-error rate of 10(-12) with a 2(31) -1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 mu m x 1796 mu m. |
URI: | http://dx.doi.org/10.1109/JSSC.2005.845970 http://hdl.handle.net/11536/13632 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2005.845970 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 40 |
Issue: | 6 |
起始頁: | 1388 |
結束頁: | 1396 |
顯示於類別: | 期刊論文 |