Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cheng, Ya-Chi | en_US |
dc.contributor.author | Chen, Hung-Bin | en_US |
dc.contributor.author | Shao, Chi-Shen | en_US |
dc.contributor.author | Su, Jun-Ji | en_US |
dc.contributor.author | Wu, Yung-Chun | en_US |
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.contributor.author | Chang, Ting-Chang | en_US |
dc.date.accessioned | 2017-04-21T06:49:14Z | - |
dc.date.available | 2017-04-21T06:49:14Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-1-4799-8000-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136351 | - |
dc.description.abstract | The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000370384800154 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |