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dc.contributor.authorLin, Yu-Hsuanen_US
dc.contributor.authorWu, Jau-Yien_US
dc.contributor.authorLee, Ming-Hsiuen_US
dc.contributor.authorWang, Tien-Yenen_US
dc.contributor.authorLin, Yu-Yuen_US
dc.contributor.authorLee, Feng-Mingen_US
dc.contributor.authorLee, Dai-Yingen_US
dc.contributor.authorLai, Erh-Kunen_US
dc.contributor.authorChiang, Kuang-Haoen_US
dc.contributor.authorLung, Hsiang-Lanen_US
dc.contributor.authorHsieh, Kuang-Yeuen_US
dc.contributor.authorTseng, Tseung-Yuenen_US
dc.contributor.authorLu, Chih-Yuanen_US
dc.date.accessioned2017-04-21T06:49:25Z-
dc.date.available2017-04-21T06:49:25Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4673-9478-9en_US
dc.identifier.issn1930-8868en_US
dc.identifier.urihttp://hdl.handle.net/11536/136432-
dc.description.abstractTMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.en_US
dc.language.isoen_USen_US
dc.titleExcellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithmen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000389022000032en_US
dc.citation.woscount0en_US
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