利用覆晶構裝設計改善氮化鋁鎵/氮化鎵高電子遷移率電晶體之特性

Abstract

由於氮化鎵基高電子遷移率電晶體可操作在高電壓及高溫環境並可輸出高電流，被視為高功率應用元件的明日之星，有極高的潛力可與傳統的金氧半電晶體競爭。 雖然打線接合仍是晶片級封裝的主流，但覆晶封裝因有較短的連接路徑及較小的封裝尺寸，因此在高頻應用方面備受矚目。事實上，覆晶封裝也非常適用於高功率元件的應用。覆晶封裝的小尺寸特性可幫助提升整體功率密度，覆晶凸塊也可幫助高功率元件的散熱。 理論上，氮化鋁鎵/氮化鎵高電子遷移率電晶體的汲極電流可透過增加異質接面的張應變而獲得提升。此外，在覆晶封裝後往往也會伴隨著熱機械應力及應變的產生。綜合以上兩點，本論文即探討如何利用不同的覆晶封裝設計，使氮化鋁鎵/氮化鎵高電子遷移率電晶體之特性提升。 本論文內容可區分為兩個部分。第一部分為單晶片覆晶封裝。氮化鋁鎵/氮化鎵高電子遷移率電晶體之壓電極化和其主動區的應變有非常大的關係。因此，透徹地了解元件通道處之應變行為對於增強電性是很重要的。此部分首先以實驗的方式探討利用覆晶封裝凸塊所造成之壓電效應進而增強元件的特性。利用材料間熱膨脹係數差，將凸塊佈局特意設計為能提供不同程度的張應變。在最佳化的主動區凸塊佈局設計下，元件之飽和電流在覆晶封裝後相較於裸晶時最高提升了 ii 4.3 %；若相較於一般傳統之佈局，改善幅度更是高達17 %。 在驗證主動區凸塊可增加氮化鋁鎵/氮化鎵高電子遷移率電晶體在通道之張應變並增強元件特性後，接下來的部分利用覆晶封裝整體結構之最佳化去調變氮化鋁鎵/氮化鎵高電子遷移率電晶體的應變狀態，進一步增加壓電效應。由模擬結果可看出通道處之等效熱機械應變會因封裝內各結構的尺寸及材料的選擇而有不同程度的影響，對於未來利用封裝設計作元件應變工程會是相當有用的資訊。 第二部分是多晶片覆晶封裝。此部分展示出利用覆晶封裝將多個氮化鋁鎵/氮化鎵高電子遷移率電晶體以並聯方式連接在功率元件應用上的潛力。裸晶及已封裝的元件皆經由脈衝式的電流電壓量測以驗證其電性及熱傳性質。三個元件經由封裝並聯後，比起裸晶時可以達到三倍的輸出電流、三分之一的導通電阻、少於五分之一的熱阻以及較低的溫度相依性。此優異的特性使得覆晶封裝成為高功率氮化鎵基電子元件應用中一個相當有潛力的技術。

GaN-based high-electron mobility transistors (HEMTs) are recognized as one of the promising candidates for applications in power electronics since they are capable of operating at high voltages and high temperatures and delivering high output currents. Hence, GaN-based HEMTs are of great potential to compete with the conventional metal-oxide-semiconductor (MOS) devices as the key components in power electronics applications. Although wire-bonding (WB) is still the main stream of chip-level packaging, flip-chip (FC) has drawn much attention especially in high-frequency applications owing to several advantages such as shorter interconnect length and smaller package size. In fact, FC packaging is also favorable for high-power applications. The compactness of FC packaging helps to increase the overall power density and the bumps can act as the paths that dissipate the heat generated by the chip. According to the theories, ID, max improvement of the AlGaN/GaN HEMTs could be made by increasing the tensile strain in the AlGaN/GaN layer. Moreover, thermo-mechanical stresses and strains will be induced after FC packaging. Combining these two characteristics, this dissertation investigates FC packaging design for performance enhancement of AlGaN/GaN high-power HEMTs. iv The content of this dissertation can be divided into two parts. The first part is about single chip FC package. The piezoelectric polarization of the AlGaN/GaN HEMTs is strongly related to its strain state in the active area. Thus, a comprehensive understanding on the strain behaviors inside the channel is important for electrical performance improvement. This part investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging. The bump patterns were designed and intended to provide different levels of tensile strain due to the mismatch in the coefficient of thermal expansion (CTE) between the materials. FC packaging with the optimized bump pattern provided a maximum increase of 4.3 % in saturation current compared to the bare die; if compared with the conventional bump pattern, a 17 % improvement was achieved. The following part illustrates the potential of optimized FC structure with active-region bumps to modulate the strain state of AlGaN/GaN HEMT for enhancing piezoelectric effect. The equivalent thermo-mechanical strain in the channel has been observed from simulated results to be affected by the package dimension and the material selection to different degrees, which will be valuable information in future packaging design for device strain engineering. The second part is about multi-chip FC package of GaN HEMTs. This part demonstrates the usage of FC packaging to connect multiple AlGaN/GaN HEMTs in parallel for applications in power electronics. The electrical and thermal properties of both the bare die and the packaged devices were investigated via pulsed current–voltage (I–V) measurements. Compared to the bare die, triple output current, one-third on-resistance (Ron), less than one-fifth thermal resistance (Rth) with temperature insensibility were observed when three transistors were connected in parallel through FC packaging. Superior performance makes FC packaging a promising technology for high power GaN electronic applications.