反轉式與無接面多晶矽奈米線環繞式閘極薄膜電晶體研究

Abstract

本研究運用簡化式側壁邊襯蝕刻技術(simplified sidewall spacer patterning technique)來定義奈米線通道(Nanowire)，藉由可簡化的平台結構設計與奈米濕式蝕刻的配合可製作出約十奈米的類單晶矽的多晶矽通道，如此可將通道內的缺陷大幅減少，接著再結合環繞式閘極結構可呈現出優異的多晶矽電晶體轉換特性。在沒有使用氨電漿處理的情況下可獲得平均約100 mV/dec的次臨界擺幅。而多通道結構的運用則可使多晶矽元件間的電特性差異呈現更穩定的表現，並獲得高的電流開關比(>109)。研究也發現在高溫的環境下，奈米線電晶體元件與微米線元件比較結果中，微米線元件因為較多的缺陷與閘極控制能力的不足，呈現電特性隨著溫度增加有比較明顯的變化，而奈米線元件則呈現較穩定的線性變化。 接著運用十奈米的多晶矽通道，研究將無接面結構(Junctionless)成功的實現在多晶矽元件上，運用環繞式閘極結構反向電場將多晶矽通道內的重摻雜載子空乏形成一電阻式開關電晶體元件，並擁有良好的電特性與高的電流開關比，經由多通道結構的運用後可達到大於1  109電流開關比，並讓無接面元件間的電特性差異變小。在多通道特性結果的比較，一般的反轉模式電晶體呈現較穩定的趨勢，我們認為這是由於在奈米線通道的寬度在蝕刻製程中產生些許偏差，而無接面元件的電特性對於通道尺寸有較強的相依性。 研究也將簡化式側壁邊襯蝕刻技術，同時應用至定義閘極長度和奈米線寬度，藉由平台結構的簡化過程，可連續的將壁邊襯蝕刻技術應用在電晶體製作流程，並獲得約十奈米的通道寬度和約二十奈米的閘極長度。為了解決在活化時造成熱擴散的問題，研究將無接面結構應用至此短通道元件，如此可以避免熱預算的問題與簡化製作流程。在多通道結構的應用上，研究發現隨著通道數量的增加到一定的數量後並沒有明顯的改善電特性的均勻性，並在各電特性均有劣化的趨勢。經由TEM結構分析我們發現，由於在閘極定義的過蝕刻而造成的底切現象，此現象將造成多通道元件容易有嚴重的短通道效應，並造成元件電特性差異的放大。在成功驗證了二次簡化的側壁邊襯蝕刻技術後，研究也提出了在製程上的改善以減少過多的串聯電阻，並分析了電晶體元件在不同奈米線長度的串聯電阻值。研究發現在經由製程上的改善後，元件的電阻值可小於10 KΩ。之後我們也對此短通道元件探討了高溫下的電特性變化，結果發現電特性的差異可藉由閘極長度的縮短降低閘極下方的晶格缺陷而變小，並且在50 nm有較好的表現。 本篇論文最後，研究將環繞式閘極多晶矽奈米線無接面電晶體應用至非揮發性記憶體元件(SONOS)，利用多晶矽通道的微縮來減少通道裡的缺陷，可因此加強了閘極對通道的掌控能力與載子穿隧至捕捉層的數量。研究發現在較小維度的奈米線通道同時擁有較快的寫入與抹除速度。可在9 V的閘極電壓施加0.1 ms的情況下達到1 V的寫入記憶體窗口大小。並在與傳統的反轉模式比較下，由於通道額外的摻雜，無接面元件呈現出較快的寫入數度。

In this study, nanowires (NWs) were defined through a simplified sidewall spacer patterning technique, with the process flow simplified by mesa structure. After being combined with a nano-wet etching process, a poly-Si NW channel with ~10 nm width was obtained. Utilizing the gate-all-around structure, the transistors showed excellent transfer characteristics as a result of the low defect density in the poly-Si channel. Without using NH3 plasma treatment, the average value of subthreshold swing can reach ~100 mV/dec. Utilizing the multiple channel structure, the difference of electrical characteristics between transistors can be reduced, and a higher Ion/Ioff current ratio (~1  109) was also obtained. The electrical characteristics of transistor devices with different channel widths were compared in a high temperature environment. Results show that the microwire (MW) transistor shows a clear change with temperature increase, which is due to larger defects and weak control of the gate over the channel. In addition, the NW device exhibits a linear relationship and smaller variations when compared to the MW device. The poly-Si junctionless transistors with a ~10 nm poly-Si NW channel were demonstrated. The carriers in the poly-Si channel were fully depleted through reverse gate bias and GAA structure, and formed a resistor-type device. The devices show excellent characteristics similar to inversion mode (IM) devices. After applying the multiple NW channel structure, the JL devices show higher Ion/Ioff current ratio (> 109) and smaller variations in electrical characteristics. However, the JL devices show larger variations than those of an IM device. This can be attributed to the fact that the characteristics of the JL device are more sensitive to variations in NW channel dimension which result from the etching process. Next, we use the sidewall spacer process to define both NW and gate structures. Through the mesa structure, the double spacer patterning process can be simplified, and a ~10 nm channel width and ~20 nm gate length were obtained. To overcome the issue of carrier diffusion in such a short channel device during thermal annealing, the JL structure was used to avoid an overly complex process and a limited thermal budget. The results show no serious short channel effects (SCEs) in our devices. However, the variations of electrical characteristics did not show significant improvement and became poorer with increasing number of channels. The undercut which can be seen at the bottom of the poly-Si gate via structure accounts for the electrical behavior. Such a behavior also led to serious SCEs and larger variations in device performance. After successful demonstrating the simplified double spacer patterning technique, we propose a modified process flow to reduce the S/D extension region and center region for lower series resistance. The total resistance of 20-nm JL devices using different NW lengths was analyzed, and the resistance reached ~10 KΩ after modifying the process flow. In addition, the JL device with a shorter gate length shows smaller sensitivity with temperature as a result of fewer defects under the poly-Si gate. Finally, we have applied the GAA poly-Si NW JL transistor as nonvolatile SONOS memory. Utilizing the scaling of the poly-Si NW channel to enhance the gate controllability over the channel, the program and erase speeds can be both improved as the channel dimension decreases. In addition, in the programming operation, a 1 V memory window can be reached at 9 V for 0.1 ms. Compared with an IM device, the JL SONOS device shows faster programming speed due to additional dopants in the channel.