應用於0.5~10GHz雜訊消除技術與電流重複利用架構之超寬頻低雜訊放大器

Abstract

本篇論文提出應用於0.5~10GHz雜訊消除技術與電流重複利用架構之超寬頻低雜訊放大器。此低雜訊放大器由兩級放大器加源極隨耦器所構成，輸入端採用電阻回授式(shunt resistive feedback)架構提供了超寬頻的阻抗匹配並增加雜訊消除(Noise cancelling)技術與電流重複利用(Current reuse)架構，可降低雜訊指數0.3~0.5dB (Noise figure)，且在不額外增加功率消耗的情況下提高放大器增益。第二級放大器使用了峰化電感架構可以提供高頻增益，並改善電阻回授式架構隔離度不佳的問題，結合第一和第二級放大器可使增益有效頻寬接近10GHz(0.1~10GHz)。最後輸出端使用了源極隨偶器作寬頻輸出阻抗匹配。 本次使用0.18-μm TSMC CMOS 1P6M製程製作，其量測結果：工作頻寬為0.5~10GHz，輸入與輸出反射係數皆小於-13dB，最大增益為17 dB，最低雜訊指數為3.1 dB，在5GHz的P1dB增益壓縮點為-19dBm，IIP3截斷點為-8.77 dBm，核心電路消耗功率為17.7 mW，整體佈局面積包含pad為0.782mm * 0.928mm = 0.725mm2。

In this paper, a two-stage Ultra Wide Band (UWB) 0.5~10GHz Low Noise Amplifier (LNA) is presented. Input stage employed shunt resistive feedback configuration with Noise cancellation technique and current re-use architecture for improve noise figure (NF) about 0.3~0.5dB and increase power gain about 3dB without increase power consumption. The common-source stage use shunt peaking technique provides high-frequency power gain to extension LNA gain bandwidth to 10GHz(0.5~10GHz). Output stage is source follow provides wideband output match. This circuit is designed in 0.18-μm CMOS process. The proposed UWB LNA achieves a maximum gain is 17dB, noise figure minimum is 3.3dB, input and output return loss are less than -13dB, IIp3 is -8.77 dBm and P1dB is -19dBm at 5GHz, It consumes 17.7mW, chip area is 0.782mm * 0.928mm = 0.725mm2.