非晶態銦鎵鋅氧化物垂直通道結構薄膜電晶體技術之研究

Abstract

非晶態銦鎵鋅氧化物已被廣泛的使用在一般水平結構的薄膜電晶體的中，近幾年半導體產業發展出新穎並受到許多關注的垂直結構短通道電晶體，卻很少有關於非晶態銦鎵鋅氧化物的垂直結構電晶體的研究。由於垂直結構電晶體比水平結構的電晶體在製程上更困難和複雜，本論文中探討如何以較穩定和簡單的方式製程出完整元件包含電極、主動層和結緣層。首先討論和分析不同種類的半導體的製程方法對於垂直結構電晶體的影響，並解決遇到的問題從中決定出對製成垂直結構，電晶體最穩定和簡單的方法。接著會討論鉬此材料作為電極對於此垂直結構，不僅可以改善電性還可以簡化和穩定製成過程中的步驟和問題。此外還研究用電漿輔助化學氣相沉積製成高品質二氧化矽絕緣層，防止過高的漏電流。最後發表目前做出非晶態銦鎵鋅氧化物垂直短通道結構的電晶體的電性並和目前僅有的一篇研究做比較。此電性為載子遷移率為 0.04 cm 2 /V．s，臨界電壓為 1.1 V，次臨界擺幅為 2.8 V/decade，電流開關比103。

Amorphous-IGZO (a-IGZO) is widely used in the planar channel thin film transistors (TFTs), but the novel nanoscale vertical structures TFTs (V-TFTs) which have attracted major attention in Si devices, were seldom analyzed by using the channel layer of a-IGZO materials. In this thesis, due to much more complicated structure of vertical channel a-IGZO TFT devices, it is necessary for vertical structure TFTs to fabricate each layer including electrodes, gate dielectric insulator, and channel layer in stable and simple processes. Firstly, the analysis of various semiconductor fabrication processes especially including etching and photolithography was described, and the optimized fabrication process of V-TFTs was presented. Next, the electrodes of Mo material used by V-TFTs can not only easily simplify the difficulty of fabrication process but also effectively stabilize the electrical characteristics of device. Additionally, the appropriate gate dielectric insulator SiO2 layers deposited by plasma-enhanced chemical vapor deposition (PECVD) were analyzed in order to suppress leakage current. Finally, the fabricated V-TFTs of characteristics with Ion/Ioff of 103, threshold voltage of 1.1 V, mobility of 0.04 cm2/Vs and a subthreshold swing of 2.8 V/decade was presented and compared to previous researches.