高遷移率通道三閘極電晶體 之靜電完整性的理論研究

Abstract

本論文針對具有薄深埋絕緣層(Buried-oxide)的三閘極電晶體(tri-gate MOSFET)提出一個次臨界解析模型。這個模型在基板電壓及深埋絕緣層厚度上展現良好的縮放性，適用於預測三閘極電晶體透過基板電壓調變多重臨界電壓的特性。透過這個解析模型，我們有效率且廣泛的探討germanium-on-insulator (GeOI) p通道三閘極電晶體的基體效應因子(body effect coefficient)。我們發現到，相對於silicon-on-insulator (SOI)而言，GeOI p通道三閘極電晶體有較佳的臨界電壓調變效率。我們的研究指出，在相同的次臨界斜率(subthreshold swing)下，要獲得相同的基體效應因子，GeOI的鰭狀通道高寬比可以設計的比較大。 利用這個次臨界解析模型與數值模擬交相驗證的方式，我們研究了GeOI p通道三閘極電晶體的本質drain-induced barrier lowering (DIBL)特性。我們發現到，相對於SOI而言，GeOI p通道三閘極電晶體除了因為有較大的通道介電常數外，還因為有一個內建的負的等效基板偏壓，導致DIBL變差。這個內建的負的等效基板偏壓最主要源自於鍺的能隙較小，因而使得源極到矽基板的功函數差較小。它會使得鍺通道中的載子較靠近通道/深埋絕緣層這個介面，而造成DIBL進一步惡化。而且這個等效基板偏壓也會影響鍺通道bulk tri-gate p-MOSFET的DIBL。因此在設計p型鍺通道三閘極電晶體時需要將這個效應考量進去。同時此效應也解釋了為何GeOI tri-gate p-MOSFET有較好的多重臨界電壓調變效率。 本論文也針對高度微縮的三閘極電晶體進一步提出一個次臨界量子解析模型。這個模型是考慮有限深位能阱以及波函數穿透(wave penetration)的情況，並利用微擾理論將短通道效應包含到模型中。這對於高遷移率三五族通道三閘極電晶體來說很重要。利用這個量子侷限次臨界解析模型與數值模擬交相驗證的方式，我們根據國際半導體技術藍圖(ITRS) 對2021年的技術預測，探討n通道InGaAs三閘極電晶體的本質DIBL特性。我們發現到，除了前述所預測的通道介電常數及內建等效基板偏壓等因素，量子侷限效應也會相當程度影響n通道InGaAs三閘極電晶體的DIBL特性。它甚至會抵消介電常數和內建等效基板偏壓所導致的負面作用，使得高度微縮的n通道InGaAs三閘極電晶體的短通道效應不如古典模型所預測的那樣嚴重。而通道長度、寬度變異所造成的DIBL之變異，也會因量子侷限效應而變小。

This dissertation provides an analytical subthreshold model for tri-gate MOSFETs with thin buried-oxide (BOX). This model shows a fairly good scalability in substrate bias (Vbs) and BOX thickness, which is crucial to the prediction of multi-threshold (multi-Vth) modulation through Vbs. In addition, we demonstrate the application of our model in multi-Vth device design for tri-gate germanium-on-insulator (GeOI) p-MOSFETs with the body-effect coefficient (γ) over a wide range of design space efficiently examined. We have shown an enhanced multi-Vth modulation behavior in tri-gate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and γ, the GeOI tri-gate p-MOSFET can possess a higher fin aspect-ratio than the silicon-on-insulator (SOI) counterpart. Through theoretical calculation by analytical solution corroborated with TCAD numerical simulation, we investigate the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate GeOI p-MOSFETs. It is found that, relative to the SOI counterpart, there exists a built-in negative substrate bias in the GeOI PFET. This built-in effective substrate bias is intrinsic to the GeOI p-MOSFET with Si substrate. It stems from the large discrepancy in the source-to-substrate work-function difference between the GeOI and SOI PFET because of the smaller bandgap of Ge, thus pulling the carriers toward the channel/BOX interface and degrading the DIBL of the GeOI PFET beyond what permittivity predicts. In addition, the built-in effective substrate bias also impacts the DIBL of Ge tri-gate PFETs on bulk substrate. This new mechanism has to be considered when designing or benchmarking tri-gate Ge p-MOSFETs. Besides, this effect also explains the enhanced multi-Vth modulation behavior in tri-gate GeOI p-MOSFETs. A quantum-mechanical subthreshold model for tri-gate devices is also proposed and verified with numerical simulation in this dissertation. The wavefunction penetration into high-k gate-dielectric and BOX has been considered, and the impact of short-channel effects on the eigen-energy has also been included through the treatment of perturbation. By using our quantum-mechanical subthreshold model together with numerical simulation, we investigate the intrinsic DIBL characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node. Our study indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. Our study may provide insights for tri-gate device design using III-V high-mobility channel materials.