實現即時的老化彈性機制藉由有效地佈署Razor Flip-Flop

Abstract

2013年國際半導體技術發展藍圖 (ITRS) [1]的預測中提到，奈米級晶片的可靠度已經高至1000 FITs (failures in a billion hours)，達到不可忽視的程度，並成為高階積體電路設計的一大挑戰，尤其是使用最先進製程生產的晶片。在設計電路時，除了滿足效能及功耗上的限制外，代表可靠度的使用壽命也必須及早納入考量。為了確保電路能有足夠高的可靠度（也就是足夠長的使用壽命），可靠度的評估以及使用壽命的優化，在當今晶片設計流程中所扮演的角色日益重要，已經成為一個必要的步驟。

造成電路效能衰減的電路老化效應，是可靠度下降的主因。一般電路老化問題的對策多在設計階段 (design time) 執行，但此階段無法準確得知實際的工作負載及操作環境等影響老化的因素。現有的少數run-time監控技術，則多是使用ring oscillator來測量操作環境參數，然後預估工作負載並推算實際的老化情形，此方式也無法獲得精確的老化分析結果。加上次14奈米製程所生產的晶片，有很高的變異性 (variability)，使得個別晶片的老化情形有顯著的差異，這也讓實際老化程度的推算難度更高。

因此我們提出一個線上(on-line/on-chip)即時(real-time)的可靠度監測機制，來準確地分析個別晶片的老化程度，再加上額外的修補技術，來改正因老化造成的錯誤運算，藉以延長晶片的使用壽命。此研究計畫的目的在於：準確地分析老化程度，避免不必要的over-design，並包含在發生錯誤時自行啟動的修補技術，使晶片的壽命得以延長。

Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, aggra-vate the aging impact and thus necessitate an aging-aware reliability verification and optimi-zation framework during early design stages. In this thesis, we propose to exploit timing spec-ulation for aging resilience, based on deploying Razor flip-flops. By formulating the problem based on Boolean satisfiability, for the first time we can determine a feasible deployment of Razor flip-flops, such that maximum degree of aging resilience can be achieved in a cost-effective manner. Experimental results show that more than 50% of aging-induced perfor-mance degradation can be recovered, while reducing the number of required Razor flip-flops by about 70%, as compared to the case of naïve Razor flip-flop deployment.