多晶矽超薄奈米帶無接面電晶體於不同基底絕緣材料之研究

Abstract

隨著3D-ICs的發展與低功率的發展，低溫製程與多晶矽材料元件被廣泛的探討。在本研究中我們在不經離子佈值與高溫活化的步驟下成功做出多晶矽超薄奈米帶無接面電晶體。此外，我們提出新穎的削薄技術：化學溶液濕式蝕刻。利用此削薄技術，我們成功讓元件通道厚度達到3奈米，並且改善其表面粗糙度。 雖然在製作多閘極結構之元件時，由於過寬的通道而使其倒塌。然而，我們卻有了重大發現：(1) 成核機制影響薄膜沉積速度，因此我們發現薄膜沉積在Si3N4 底材上會得到較厚的膜厚。(2) 成核機制影響薄膜品質，透過材料分析我們可以發現沉積在Si3N4底材上的薄膜會較粗糙。(3) 通道厚度嚴重影響元件特性，隨著厚度增加元件能有更高的電流與性能。 經由本研究探討後，我們得知，比起一般傳統MOS元件，無接面電晶體更具未來發展性，因其具有良好的S.S.及DIBL。在底材的探討上，我們得到在TEOS底材上之薄膜會有較好的特性，因其在製程時產生較少的晶粒。無接面電晶體製作在TEOS底材上不僅有良好的S.S. 及DIBL，其臨界電壓具有調變性且有良好的開／關之電流比。 由此可知，無接面電晶體製作在TEOS底材上在低功率與3S-ICs之發展上極具潛力。

For the applications of low-power and monolithic 3D-ICs demand, to develop the low-temp poly-Si is an urgent study. In this study, a very simple method for junctionless (JL) ultra-thin nano-belt transistors has been successfully demonstrated by an implantation-free technique. Furthermore, the novel thin down technique (chemical solution wet etching) has been proposed. The nano-belt thickness successfully thin down to 3nm by chemical solution. Though the double gate structure collapsed during the fabrication, several finding as follows: (1) depositing rate cause by nucleation rate. The thin film deposited on Si3N4 has thicker film. (2) quality of thin film cause by nucleation mechanism. Through the materials analysis of AFM, we find that the thin film deposited on Si3N4 is rougher. (3) device characteristic cause by nano-belt thickness. As the nano-belt thickness increase, the higher on-current without off-current increasing. As the result of the thesis, JL is the promising candidate for the development owing to its good characteristic of S.S. and DIBL. JL deposited on TEOS (JL_O) underlying material is better than on Si3N4 due to less grain boundary in the channel. JL_O not only has good S.S. and DIBL but also has the modulation of threshold voltage and high on/off current ratio. JL_O is a promising candidate for low power and 3D-ICs application.