以氧化鎢電阻式記憶體探討影響寫入干擾錯誤時間變因之研究

Abstract

在本篇論文中，我們研究在氧化鎢電阻式記憶體操作過程當中，哪些因素會使寫入干擾錯誤所需時間劣化，並詳細地探討這些變因與寫入干擾錯誤所需時間之間的關係式，以下我們研究的變因有三種，分別是元件的低阻態電流大小、寫入干擾的偏壓大小、以及元件操作的環境溫度。 我們證明元件在越大的低阻值狀態電流下，高阻值狀態下的寫入干擾所需時間有很明顯縮短的趨勢，而這樣的結果我們認為跟導電燈絲的橫切面面積大小有關，此外我們利用三維的蒙地卡羅模擬修正了一維的面積公式。 另外我們也證明元件在越大的寫入干擾偏壓以及操作的環境溫度下，寫入干擾所需時間一樣會有很明顯下降的現象，最後我們分析實驗數據，萃取出我們元件的活化能，與其他研究對照之下是很合理的結果。

In this thesis, we investigate the factors affecting SET-disturb failure time in a tungsten oxide resistive switching memory and research the formula in detail. The factors are current level of low resistance state, magnitude of SET-disturb voltage and operation temperature. We prove that the SET-disturb failure time in high resistance state would degrade drastically as we raise the current level of low resistance state. To explain this phenomenon, we assume that the lower LRS resistance level has a residual conduction filament of a larger cross-section. We also partly correct the one-dimensional analytical model with three-dimensional Monte Carlo simulation. Besides, we can observe that the SET-disturb failure time will shorten as we raise the disturb voltage and the setting temperature, and the extracted activation energy seems reasonable compared with previous study.