時間交錯式類比數位轉換器及其校正技術

Abstract

當今世界正處於信息時代的高速發展階段，因此對於電子信息硬體的精度、速度等的性能指標也有了越來越高的要求。在數據轉換器方面，相較於因製程等因素而有著速度提升瓶頸的單通道類比數位轉換器，能夠隨著通道數的增加而增速的時序交錯式類比數位轉換器越來越受到歡迎。並且時序交錯式類比數位轉換器的動態功耗並不會隨著速度的提升而成倍數的增加。不過對於時序交錯式類比數位轉換器的多通道架構而言，失調失配、增益失配、帶寬失配、時序歪斜等產生的非理想效應會嚴重影響模數轉換器的性能，關於這些非理想特性的電路設計和校正技術也因此成為學術界和產業界的研究熱點。 本文從時序交錯式類比數位轉換器的取樣模式和級間失配等方面入手，詳細分析時序交錯式類比數位轉換器系統的相關特性並進行建模模擬。繼而對學界業界已有的校正失調失配、增益失配的累加平均技術、隨機斬波技術、校正非線性、校正時序歪斜的偵測與校準等相關技術細節展開分析與比較。 為了適用於直接對時序交錯式類比數位轉換器的數位輸出做處理而無需回調原有的類比數位轉換器電路的應用情形，本文設計一種針對各種非理想效應的全數位的背景偵測與校準技術。經過失調失配、增益失配、非線性、時序歪斜等的逐級校正，將含有實際的時序交錯式類比數位轉換器的數位輸出校正到相對準確的數位輸出。

Today, the world is in the information age of a rapid development stage, the requirements of electronic hardware on accuracy, speed and other performance have also been increasingly higher and higher. For data converters, the single-channel analog-to-digital converters (ADC) have a speed-boost bottleneck due to process and other influencing factors. So the time-interleaved analog-to-digital converters which capable of increasing speed with the number of channels become more and more popular. And the dynamic power consumption of the timing interleaved analog-to-digital converters will not increase multiple with the increasing speed. However, non-ideal effects for multi-channel ADCs such as offset mismatch, gain mismatch, bandwidth mismatch, timing skew, etc., can seriously affect the performance of timing interleaved ADCs. Circuit design and calibration technologies for these non-ideal characteristics have become a hot topic in academia and industry. In this paper, the characteristics of the time-interleaved ADC system are analyzed in detail from aspects such as sampling mode and inter-stage mismatch of time-interleaved ADCs and a model has been designed for simulation. Then we analyze and compare the technical details such as the average calibrations for offset mismatch and gain mismatch, the random chopping technique, the nonlinearity calibration and the detection and correction of the timing skew calibration. In order to apply directly to the digital outputs of the digital-to-analog converter without adjusting the original ADC circuits, we designed an all-digital background detection and correction technology for a variety of non-ideal effects. After the step-by-step calibrations of offset mismatch, gain mismatch, nonlinearity, timing skew, etc., the actual time-interleaved ADC digital outputs are calibrated to the relatively accurate digital values.