適用於多重天線系統之廣義幾何平均分解處理器

Abstract

廣義幾何平均值分解 (Generalized geometric mean decomposition (GGMD))將一個比較大的矩陣拆解成較小的矩陣，並且分層對拆解過後的小矩陣進行幾何平均值分解 (Geometric mean decomposition (GMD))，此篇論文實現了一個廣義幾何平均值分解處理器，可以支援矩陣大小為1到16中$2^n$的情況。在硬體架構設計上，會以此運算複雜度最低最低為考量去設計廣義幾何平均值分解處理器。因為coordinate rotation digital computer (CORDIC)在硬體實現上較為簡單，因此在此晶片設計中，許多運算使用CORDIC為基本運算單元。這篇論文所提出的廣義幾何平均值分解處理器採用90 nm CMOS製程實現，可以支援 2x2 到 16x16 中 2^n 的情況的矩陣分解，實現面積為1.96 mm^2 ，邏輯閘數為230.3K。在操作頻率為125MHZ以及供給電壓為1V的情況下所消耗的功率為1.4-15.2mW，吞吐量在 16x16 的情況下達到249K matrices/sec。

In the generalized geometric mean decomposition (GGMD) algorithm a matrix is decomposed as several smaller matrices, and geometric mean decomposition (GMD) is conducted separately for each. A GGMD processor is proposed in this thesis. For hardware implementation, the computational complexity of the proposed GGMD algorithm is analyzed in GMD units, and the decomposition method with less computational complexity will be implemented as a flexible GGMD processor. Many required computations are implemented using coordinate rotation digital computers (CORDICs) because of their low hardware complexity and diverse functionality. The proposed GGMD processor supports matrix sizes are 2^n and from 2x2 to 16x16. The chip integrates 230.3K gates in an area of 1.96 mm^2 based on 90 nm CMOS technology. The maximum throughput is 249K matrices/sec for a 16x16 matrix at 125MHz. It dissipates 1.4-15.2 mW at 125MHz from a 1V supply. This approach supports GGMD for larger matrices with reduced power consumption.