VLSI漏電區域的定位與解析

Title:	VLSI漏電區域的定位與解析 The Location and Root Cause of the VLSI Leakage Path
Authors:	穆劍龍吳耀銓 Mu, Chien-Lung Wu, Yew-Chung 工學院半導體材料與製程設備學程
Keywords:	失效分析;電性分析;漏電;OBIRCH;InGaAs;Thermal emmi;ASIC;IP;Fourier Transform
Issue Date:	2017
URI:	http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070261302 http://hdl.handle.net/11536/140275
Appears in Collections:	Thesis