三維積體電路關鍵技術及其製程平台開發

Abstract

本博士論文研究三維積體電路關鍵製程技術，內容致力於研發三維積體電路平台來克服當今三維積體電路所面臨的昂貴製程。在此研究中，將採取三個面向來進行，其中包括銅矽直導通孔(Cu TSV)的製作、接合技術、可測性技術。藉由改善傳統三維積體電路所面臨的技術性的困難及在低成本設備的基礎上發展因應的解決方案來達成其平台的建置。 首先，在銅TSV的製作上，於傳統TSV製程下，介紹及發展出氧化矽TSV及高分子TSV兩種截然不同絕緣材料下的Cu TSV 製程。由於在三維積體電路製程中，金屬化製程(含TSV、金屬繞線、金屬凸塊)佔整體成本最大比例，探討其銅柱的製作方式將有助於低成本技術的研發。然而，在研究TSV電阻時，發現傳統的銅TSV電鍍製程將引起嚴重的缺陷-電阻變異 (Resistance variation)。此現象顯示TSV的電鍍會隨著其擺放的方式與密度的不同而產生不同大小的孔洞於銅柱中，這將會造成後續電路應用上的困難。因此，為了解決此問題及在於低成本的考量下，研發出嵌縫佈線 (Sealing RDL) 以取代傳統電鍍方式。此方法藉由RDL形成背部電極(bottom metal electrode)的方式，來達到銅由下往上的導孔填充 (bottom up)。除此之外，此方法提供TSV 與RDL的共成長模式來達到製程的簡略。為了偵測其製作品質，在電性量測上，設計出單一Kelvin 結構、Daisy chain結構、Comb 結構來了解其阻質、電容與漏電流；在可靠度測試中，藉由濕度測試和高溫循環變化來測試結構的穩定性。分析結果顯示該製程可提供良好電性結果及其高可靠度結構。 在金屬接合製程上，藉由發展C2W金屬薄膜接合(Metal electrode bonding)以省略金屬凸塊製程(Bump-less)來達到製程成本的降低。其中的關鍵技術為單邊加熱技術的研發。由於金屬薄膜在傳統的C2W的接合製程中，會有氧化的現象，造成製作上的困難。因此，本研究研發出於280℃單邊加熱來達成銅銦C2W的製程。研究結果顯示，單邊加熱確實可克服雙邊加熱所造成阻質上升的困難。除此之外，為了提供大量的生產速率，短時間接合製程也透過整片晶圓接合後的退火方式成功研發並通過可靠度的測驗。 基於無金屬凸塊製作(bump-less)與背部電極(bottom metal electrode)可達低成本製程的概念，更進一步將其應用於三維積體電路中的異質結構製作。藉由使用底部傳導線來形成底部佈線和背部電極的方式，可在完成高分子接合後，成功由之前研發的Sealing approach進行銅柱電鍍。此研究中，提供兩種製作方式-via-coating based process及Cu/SU-8 based damascene process，並將其中所遭遇的困難進行分析解決；其中包括SU-8 shrinkage，via chocking 和 Cu growth out。最後，可得其良好的製作良率與電性特性。 最後將探討可測性測試對於三維積體電路的成本影響，其中堆疊誤差對於已堆疊完成的三維積體電路影響甚鉅，然而堆疊誤差電性測試的結構卻少有研究且深具挑戰。因此，本研究成功研發出以電性的方式偵測堆疊接合後所造成的對準誤差。其中包含了位移量(translation)、旋轉量(rotation)和因熱膨脹係數差異所造成的誤差量(run-out)。除此之外，也建構出了電路架構以便減少量測用之TSV數目。整體而言，本研究著重於三維積體電路相關技術之改善與研發，以提供可以使用簡易製程及設備來製作三維積體電路之結構為首要精神，來達成低成本製程的研發。

In this thesis, three-dimensional (3D) integration is designed, fabricated and investigated on electrical characteristic and reliability. For implementation of 3D integration in high-volume manufacturing, this research demonstrates a low cost fabrication platform based on three prospective, including fabrication of TSV, bonding technology, and stacking fault testing. Process of oxide based TSV and polymer based TSV are introduced and developed for the TSV fabrication part. To achieve low-cost fabrication, metallization of TSV, which is the largest proportion in 3DIC fabrication cost, needs to be investigated in detail. However, even with properly formed TSVs, an effect known as “resistance variation” is discovered in designed structure. The results show that the resistance of chain increases when there are dummy TSVs located near the chain. It implies that the conventional Cu plating method will induced void formation caused by different density and arrangement resulting in different RC delay in 3DIC design. Therefore, a new plating approach is developed for low cost fabrication to overcome the issue of resistance variation. Thus, a sealing redistribution layer (RDL) approach is proposed to utilize the bottom metal electrode method, which is different from the top-down method used in conventional plating. In order to avoid void formation, bottom RDL can be co-fabricated with TSV, reducing the fabrication steps. In this concept, bottom RDL is not only served as a TSV bottom metallization but also bottom metal electrode for plating. This concept can avoid bottom Cu removal in conventional bottom electrode approach, reducing the fabrication cost. To inspect quality of TSVs from this new method, Kelvin, daisy chain, and comb structure are designed to obtain electrical characteristic including resistance, capacitance and leakage. In addition, thermal cycle test and humidity test are performed to check its reliability. The results show that the proposed sealing approach can be a potential candidate for low cost fabrication in 3Dintegration. In the research of metal bonding, metal electrode (metal film) bonding can avoid the fabrication cost of μ-bump and meet the requirement of miniaturization. However, in C2W fabrication, there is an issue of metal oxidation on the bottom wafer. To solve this, single-sided heating approach, which ensures that only the chip side is heated during the bonding process, is developed. Compared with double-sided heating approach, proposed method indeed can avoid thin film metal from oxidation during C2W bonding. In addition, with the help of post-bonded annealing, proposed approach can have shorter bonding time with high quality. Based on the above results, bottom electrode approach using sealing RDL and bump-less bonding are essential to reduce cost fabrication. Therefore, a bump-less scheme using bottom conducting lines served as bottom electrode and bottom RDL is proposed to obtain hybrid structure in 3D stacked chips/wafers. With only polymer adhesive bonding involved, the fabrication can be achieved by using via-coating process or Cu/SU-8 damascene process. The issues during the process such SU-8 shrinkage, via chocking and Cu growth out, are discussed in detail and solved. Finally, high yield of fabrication with good electrical performance can be obtained. Finally, a novel testing structure for stacking fault is proposed. By placing several metal lines with fixed pitch around bottom electrode, the number of short/open circuit path between top electrode and metal lines created after metal electrode bonding or Cu seed layer deposition can reveal the quantity of misalignment. In addition, different stacking faults including rotation, run-out and translation and one time measurement with minimum active region consumption are also investigated. At the end of this thesis, conclusions as well as prospects for further studies are given.