考慮時脈偏移的功能時序分析引擎與建立時間違反的應用

Abstract

時脈偏移(clock skew)對於現今電路設計的影響越來越重要，儘管之前的許多研究已經提出以傳統靜態時序分析(static timing analysis)或統計靜態時序分析(statistical static timing analysis)考慮時脈偏移效應，邏輯錯誤路徑的存在會導致電路最佳化的過程中多了不必要的成本。因此，為了更精確地計算出電路的最大延遲時間，我們提出一個先進的考慮時脈偏移的功能時序分析引擎(Sk-FTA Engine)，基於功能時序分析(functional timing analysis)方法來考慮時脈偏移效應，可以避免錯誤路徑在延遲時間估計上帶來的悲觀。此外，我們用考慮時脈偏移的功能時序分析引擎檢查建立時間(setup time)違反(violation)，過濾發生在錯誤路徑上多餘的違反情況。實驗結果顯示出在最佳例子(電路s13207)上，Sk-FTA計算出的最大延遲時間比原本的FTA改善了51.69%。對於大部分的電路，建立時間違反的數量也大幅地減少，其中，vga_lcd電路以考慮時脈偏移的靜態時序分析(skew-aware STA)方法檢查出的512個違反情況，全部都會被Sk-FTA消除。

Clock skew is an increasing concern in modern VLSI designs. Although several works have been proposed to deal with the clock skew in STA and SSTA, existence of (functionally) false paths induces unnecessary cost during design optimization. Therefore, for accurately computing the critical timing for the target design, we propose an advanced engine named Sk-FTA, capable of handling the clock-skew effect and avoiding the pessimism of false paths on basis of functional timing analysis (FTA). Moreover, Sk-FTA is used to check setup violation and filter redundant violations on false paths. Experimental results show that the reduction ratio between our improved framework and the original one can be 51.69% for the best case (s13207). The number of setup violations also is reduced significantly for most of the benchmark circuits. In particular, for benchmark vga_lcd, the original 512 violations reported by skew-aware STA are reduced entirely by our Sk-FTA framework.