标题: | 侧壁镶嵌三闸极多晶矽鳍式电晶体应变效应之研究 Strain Effects on Sidewall Damascened Tri-Gate Poly-Silicon Fin-FETs |
作者: | 王泓翔 赵天生 Wang, Hung-Hsiang Chao, Tien-Sheng 理学院应用科技学程 |
关键字: | 应变效应;多晶矽;鳍式电晶体;无接面电晶体;Strain effect;Poly-Silicon;FinFET;Junctionless transistor |
公开日期: | 2016 |
摘要: | 近年来随着可携式电子产品蓬勃发展到人手可见,然而可携式电子产品中扮演重要关键角色的积体电路元件通道也持续微缩进入奈米等级尺寸,也因为元件通道持续微缩逼近物理极限所面临到短通道效应、漏电及微影制程等问题,为了克服上述的问题在电晶体结构上必须由传统二维平面式演进到新颖三维立体式的世代,因此三维立体鳍式场效电晶体 (Fin-FET) 在近年来被广泛研究及讨论。 在此篇论文中,我们提出新颖氮化矽/二氧化层/氮化矽 (Nitride/Oxide/Nitride) 三明治结构与侧壁镶嵌技术 (Sidewall Damascened Technique) 制作出无邻近应变技术 (Strain Proximity Free Technique) 及应变记忆技术 (Strain Memorize Technique) 两种不同应变效应的侧壁镶嵌三闸极多晶矽鳍式电晶体技术 (Strain Effect on Sidewall Damascened Tri-Gate Poly-Si FinFETs),利用湿式选择性蚀刻直接蚀刻出鳍式通道, 制程中无须透过先进曝光机台制作出具备鳍式场效电晶体,在结合临场掺杂之技术 (In-Situ Doped) 搭配制作出无接面式并具备应变效应的矽奈米鳍式场效电晶体,此种电晶体拥有良好电性特性如临界摆幅、漏电流控制、开关电流比值及载子迁移率,具备以上优势预期在未来闸极长度在持续微缩过程中将更具发展的潜力。 Recently the booming of portable electronic products are part of people’s everyday live. Nevertheless, the channel dimension of integrate circuits devices aggressively shrink into nanometer-scales. The integrate circuits are participate as key component of portable electronic products. because of continuously shrink of the channel dimension which near physical limitations had induce short channel effect, leakage and require expensive lithography tools are become a serious events. The current conventional planar transistor structure has revolutionized from two-dimensional to novel three-dimensional generation. This novel three dimension architecture able to conquer aforementioned events. Accordantly the enhancement of three-dimensional architecture Fin-FET had been considered extensive in many research and discussion. In this thesis, we propose a novel nitride/oxide/nitride sandwich structure by selective etch define fin shape channel. The process using innovative sidewall damascened technique without any advance lithography tools. With this sandwich structure we can easily implement strain proximity free technique to fabricated high performance transistor. Finally employ in-situ n+ doped the junctionless fin field effect transistor with strain effect are successfully demonstrated. This junctionless transistor exhibit excellent device characteristics of low subthreshold swing, low off state leakage current, high on/off ratio and high carrier mobility. A significant performance improvement had advantage and continuously shrink of the gate length will be the promising candidate in the future. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070252907 http://hdl.handle.net/11536/140729 |
显示于类别: | Thesis |