具製程電壓溫度補償之非晶體震盪器電路設計與實現

Abstract

隨著半導體製程進步，低操作電壓電路之應用逐漸隨半導體進步而日趨盛行，而其中最無法降低電壓部分為晶體振盪器。其有穩地性極佳但必須操作在高操作電壓之工作環境之特性。因此，無晶體振盪器之可行性日趨重要，但低操作電壓伴隨著電路操作頻率增快、處理資料量增加，引發劇烈系統晶片溫度變化，降低電路穩定性、造成資料錯誤等缺點。為了避免上述問題產生以及搭配低電壓電路設計，系統晶片整合時需規劃於電路中一溫度製程補償電路，作為監測並管理晶片溫度於安全範圍內。因此低成本、高精準度之無晶體頻率產生器已成為近年積體電路相當熱門之研究議題。 傳統類比式無晶體振盪器利用疊接方式做操作電壓之補償，並利用BJT作為穩定溫度之能帶隙參考電壓電路。然而此些方式並無法利用在低電壓之溫度補償架構上主要為BJT之可驅動電壓遠大於低電壓之操作電壓。此種溫度補償電路為具有高解析且高精準度之溫度補償電路。但由於電路功率消耗大、晶片面積大、轉換率低、製成與電壓限彈性度低等缺點。使得傳統式溫度補償電路於低電壓應用時，有許多限制與成本過高的問題。 為改善上述類比式溫度感測器缺點，本篇提出低電壓操作電路，利用基極操作電壓，次臨界區MOSFET操作元件，以及-gm增益放大技術來使得操作於低電壓趨為可行。實現具有功率消耗低、晶片面積小、設計複雜度低與系統相容度高之溫度補償電路，改善了傳統式溫度補償電路之缺點。但是電路特性與應用規格之不同，目前尚未有人達到低電壓頻率飄移精準之無晶體頻率產生器。 本篇論文主要提出共兩顆不同的具溫度電壓頻率補償之無晶體震盪器，一為具八個相位輸出，本電路實現於TSMC 18um混合訊號製程，供應電壓為1.8伏特並以環型震盪器為基底，採用兩點校正的方式，並找出所在之製程及溫度飄移後，使用簡易類比方式進行線性度修正增加量測精準度，提供具溫度製程補償之準確輸出。並在於面積極小的情況，達到相位間誤差小於5.5%以及duty Cycle 誤差小於4.3%，經修正後溫度係數為小於70ppm/℃，八相位頻率為192MHz之輸出頻率。 另一顆為超低壓具溫度補償之無晶體頻率產生器，本電路實現於TSMC 65nm混合訊號製程，供應電壓為0.5伏特，並提供一不具頻率電壓溫度影響且其輸出頻率為2.4GHz 之時脈，前端以環型振盪器及LC壓控震盪器以及數位電路構成製程選擇電路，校正頻率產生器因製程變異引起的偏移誤差。經選擇製程後由查看設計好的比較表後再經溫度補償。以低電壓的能帶隙電壓產生電路以及低電壓之溫度控制器產生一部隨溫度以及製程影響之電路；功率消耗為2.5mW/sample，操作溫度0°C~ 100°C，經查表修正後頻率誤差為33.47 ppm/℃。 本研究將以類比式無晶體頻率產生器之方法為主，保留原有之優點並朝高精準度補償為設計目標，以達到頻率飄移為50 ppm/℃ 之規格。此外傳統文獻中為了提高精準度於量測時採用兩點校正(two point calibration)之測試方法，增加了許多測試成本，此問題亦為本研究探討要點之一。 此外。為了維持論文的完整性，附錄A並收錄了利用了TCAD軟體模擬討論背電極對非晶體氧化銦鎵鋅(amorphous IGZO)之空乏層的影響，因為電子空乏效應，在高的功函數的背金屬下，電子都被金屬移走，而此行為導致了臨界電壓的增加，而利用了TCAD軟體的模擬，可發現增加通道長度以及減少厚度可以有效地增進此效應。而附錄B收錄了作者於博士班期間發表的另一篇有關玻璃基板的參考電壓電路。

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs is operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators has been studied. A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed in Chapter 3. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18 m CMOS process for digital power management systems. A temperature-calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65m ×75m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/°C from 0 to 100°C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of −102dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively. Being operated with 0.5V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated crystal-less clock generator. The bias current provided by the bandgap reference circuit and low-dropout operate amplifier are nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated crystal-less clock generator functions well by the analog linear compensation mechanism. Chapter 4 presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance. We also discuss the time to digital converter system for time measurement unit in chapter 5. The Appendix A shows the electron distribution in an amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistor (TFT) with a floating metal–semiconductor (MS) back interface is analyzed using a technology computer-aided design (TCAD) model. The channel geometry (i.e., length and thickness) effect is carefully investigated. At a high work function (i.e., 5 eV) of the capping metal, the capping metal (electron depletion effect) mostly removes electrons inside a-IGZO. The depletion of the IGZO film leads to an increase in threshold voltage in a-IGZO TFT. TCAD simulation reveals that increasing channel length and decreasing IGZO thickness significantly enhance such an electron depletion effect. Finally, the electron depletion effect is applied to a-IGZO TFT with a high-conductivity IGZO film to greatly suppress the leakage current by over 5 orders. The Appendix B shows a voltage reference circuits on poly-Silicon TFT. Because this paper is based on author’s master thesis, detailed contents could refer the author’s master thesis.