增進嵌入式中央處理器漏電估計準確性

Abstract

先前文獻利用晶片上溫度感測器估計中央處理器靜態漏電，然而嵌入式中央處理器通常只搭配一個或少數的晶片上溫度感測器，並且中央處理器晶片上會有巨大的溫度變異，因此，透過晶片上的溫度感測器來估計靜態耗電會造成顯著的誤差。根據我們的實驗，傳統的靜態耗電估計方法在70nm的嵌入式中央處理器上會造成高達22.9%的估計誤差。在此研究當中，我們先評估利用擺放在晶片不同位置的溫度感測器對於估計靜態耗電的準確性，並且建議溫度感測器擺放的位置，此位置可以將誤差降低至0.9%。再來，我們提出了一個 temperature-referred and counter-tracked estimation (TRACE) 模型，利用原本的溫度感測器配上硬體活動計數器來估計靜態耗電。模擬的結果顯示利用 TRACE 模型可以將誤差降低到 3.4% 以下。我們透過模擬的環境以及真實的平台來驗證我們的發現。

Previous studies have used on-chip thermal sensors (diodes) to estimate the leakage power of a CPU. However, an embedded CPU equips only a few thermal sensors and may suffer from considerable spatial temperature variances across the CPU core, and leakage power estimation based on insufficient temperature information introduces errors. According to our experiments, the conventional leakage power models may have up to 22.9% estimation error for a 70-nm embedded CPU. In this study, we first evaluated the accuracy of leakage power estimates based on thermal sensors on different locations of a CPU and suggest locations that can reduce the error to 0.9%. Then, we proposed the temperature-referred and counter-tracked estimation (TRACE) model that relies on temperature sensors and a hardware activity counter to estimate leakage power. The simulation results demonstrated that employing TRACE could reduce the error to 3.4%. Experiments were also conducted on a real platform to verify the accuracy of our findings.