應變閘極堆疊負電容鐵電介電層應用於低功耗記憶體與次10奈米電晶體之研究

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	邱于建	zh_TW
dc.contributor.author	張俊彥	zh_TW
dc.contributor.author	鄭淳護	zh_TW
dc.contributor.author	Chiu, Yu-Chien	en_US
dc.contributor.author	Chang, Chun-Yen	en_US
dc.contributor.author	Cheng, Chun-Hu	en_US
dc.date.accessioned	2018-01-24T07:40:10Z	-
dc.date.available	2018-01-24T07:40:10Z	-
dc.date.issued	2017	en_US
dc.identifier.uri	http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070380111	en_US
dc.identifier.uri	http://hdl.handle.net/11536/141054	-
dc.language.iso	en_US	en_US
dc.subject	鐵電	zh_TW
dc.subject	負電容	zh_TW
dc.subject	氧化鋯鉿	zh_TW
dc.subject	非揮發性	zh_TW
dc.subject	記憶體	zh_TW
dc.subject	ferroelectric	en_US
dc.subject	negative capacitance	en_US
dc.subject	HfZrO	en_US
dc.subject	nonvolatile	en_US
dc.subject	memory	en_US
dc.title	應變閘極堆疊負電容鐵電介電層應用於低功耗記憶體與次10奈米電晶體之研究	zh_TW
dc.title	Strained-Gate with Negative Capacitance Ferroelectric Dielectric Layer for Energy Efficient Memories and Sub-10nm Transistors	en_US
dc.type	Thesis	en_US
dc.contributor.department	電子研究所	zh_TW
顯示於類別：	畢業論文