三維積體電路之超薄緩衝層技術於銅/錫接合研究及開發

Abstract

銅/錫接合結構受限於金屬間的快速相互擴散而無法降低銲錫用量。為了解決這個問題，本篇論文使用超薄緩衝層於銅錫次微米薄膜接合，以減緩共晶接合前的相互擴散現象。為了提高未來實際應用的多元性，不同材料(鎳、鈷、鈦、鈀)及不同厚度(10 奈米至100奈米)的超薄緩衝層會分別在這篇論文中被討論。為了評估超薄緩衝層的緩衝能力，我們藉由歐傑電子能譜儀進行元素縱深分析觀察銅錫相互擴散程度。研究結果成功開發出使用鎳或鈷為超薄緩衝層的晶圓級銅錫薄膜共晶接合。除了接合強度測試以外，本研究除了利用多種材料分析手法探討其接合品質，並且經由電性特性及可靠度測試，發現此接合結構不只表現良好的晶圓級均勻性，並且對高熱應力、高濕度具有良好的可靠度。除此之外，使用超薄緩衝層應用於非對稱銅錫-銅接合的結構也被成功開發，並且展現較對稱銅錫接合結構更好的可靠度特性。 綜合以上，超薄緩衝層的多元應用價值可望在未來被應用於先進三維積體整合。

In order to achieve submicron Cu/Sn bonding to keep up with the trend of transistors scaling, a particular ultra-thin buffering layer (UBL) is inserted between Cu and Sn to delay the interdiffusion before eutectic bonding. Various different materials and thickness ranging from 10 nm to 100 nm of UBL are thoroughly studied in this research. To increase the flexibility of this Cu/Sn bonding scheme for advanced 3D integration application, some CMOS compatible materials including Co, Pd and Ti are also discussed. Successful wafer-level Cu/Sn bonding with Ni UBL and Co UBL are demonstrated. Several kinds of material analysis are conducted to evaluate the bonding results while the buffering ability of the different materials are evaluated by Auger depth profile analysis. In addition to symmetric Cu/Sn bonding with UBL, asymmetric Cu/Sn-Cu bonding with Ni UBL, which is found with better reliability, is also demonstrated. With electrical performance examination and reliability tests (TCT and HAST), Cu/Sn bonded structures with UBL show not only an excellent uniformity on wafer-level but also good reliability. Above all, the application of UBL used in soldering technology gives a promising and flexible platform for future 3D integration applications.