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dc.contributor.authorChin, Ching-Yuen_US
dc.contributor.authorTsou, Yao-Teen_US
dc.contributor.authorChang, Chi-Minen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2014-12-08T15:19:57Z-
dc.date.available2014-12-08T15:19:57Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4868-5en_US
dc.identifier.issn1089-3539en_US
dc.identifier.urihttp://hdl.handle.net/11536/14134-
dc.description.abstractThe NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package testing instead of in its wafer testing, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.en_US
dc.language.isoen_USen_US
dc.titleA Novel Test Flow for One-Time-Programming Applications of NROM Technologyen_US
dc.typeArticleen_US
dc.identifier.journalITC: 2009 INTERNATIONAL TEST CONFERENCEen_US
dc.citation.spage177en_US
dc.citation.epage185en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000279591000021-
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