NROM資料保存能力之研究

Abstract

當快閃記憶體的發展邁向十億位元領域的同時也面臨到許多的挑戰，這些挑戰限制了元件面積的縮小。傳統的浮動閘快閃記憶體所面臨的最大挑戰就是穿隧氧化層的厚度無法再做進一步的微縮，根據記憶體元件的物理特性與電性特性研究，再使用外差法來推算，浮動閘快閃記憶體的製程極限大約可以到達45奈米。與浮動閘快閃記憶體相比之下，SONOS結構的快閃記憶體擁有較佳的製程微縮能力與簡單的製程。SONOS結構的快閃記憶在經過資料的寫入與抹除的操作之後，在寫入的狀態下會發現到電荷的損失，而在抹除的狀態下會發現到電荷的增加。這些變化都會影響記憶體元件資料保存的正確性。 本論文研究NROM(Saifun公司所發明的SONOS結構的快閃記憶體)在抹除狀態下如何降低儲存電荷的增加。在研究中我們發現到護層中的水氣是影響抹除狀態時電荷增加的關鍵。製程中殘留的水氣會加速熱電子效應所導致的元件退化，熱電子效應會使得被補抓在底層氧化層中的正電荷增加。所以我們藉由降低護層中的水氣含量以及避免水氣擴散到元件這兩種方式來改善抹除狀態時的電荷增加。 在降低水氣含量的實驗中，我們發現在SAUSG沉積之後將晶片在420℃的溫度下烘烤30分鐘可以讓抹除狀態的臨界電壓飄移由1.6V降低為0.2V。即使在較差的護層結構下也可以得到相當好的資料保存能力的改善。 在避免水氣擴散到元件的實驗中，將第一層護層的材料由低功率電漿化學沉積的二氧化矽換成氮化矽可以讓臨界電壓飄移由1.6V降低為0.3V。將介層阻障層中鈦的厚度由15奈米增加到40奈米可以讓臨界電壓飄移由1.7V降低為0.3V。綜合這兩種改善，不但可以讓臨界電壓飄移維持在0.3V以下，還可以使沒有產生臨界電壓飄移的實驗樣本超過30%。 在這些實驗中，抹除狀態下的電荷增加可以獲得大幅改善。這些改善使得元件在經過寫入與抹除的操作之後，讀取”1”的資料空間變得更大，進而改善了資料保存能力。使得NROM有機會從多次寫入的記憶體變成真正的快閃記憶體。

As flash memories move toward giga-bits era, several challenges limit their scalability. The major problem of floating gate flash memories is un-scalable tunnel oxide. Although SONOS (Silicon Oxide-Nitride-Oxide Silicon) type flash memories show better scalability and simpler process, there are still some difficulties. Both charge gain at erase state and charge loss at program state after cycles will diminish read window and finally decrease data retention after cycling. In this study, charge gain at erase state was investigated. In the investigation, we found moisture in passivation layer is the key factor to affect charge gain at erase state. The moisture will increase positive charge trapped in bottom oxide of NROM (NROM is a registered trademark of Saifun) memory. Reduce moisture in passivation layer and prevent moisture diffuse to memory cell is investigated to reduce charge gain at erase state. To reduce moisture in passivation layer, we bake experiment wafer at 420℃ for 30min after SAUSG (Sub Atmosphere Undoped Silicate Glass) film deposition. The threshold voltage shift at erase state can decrease from 1.6V to 0.2V even with worst passivation film structure. To prevent moisture diffuse to memory cell, change first passivation film material from low power plasma enhanced oxide to silicon nitride can reduce erase state threshold voltage shift from 1.6V to 0.3V. Increasing titanium thickness in via barrier from 15nm to 40nm can lower threshold voltage shift from 1.7V to 0.3V. Combine passivation film modify and increase titanium thickness not only threshold voltage shift can keep under 0.3V no threshold voltage shift samples also can exceed 30%. Charge gain at erase state was greatly improved in these investigates. The enlarged of read “1” window can improve data retention after cycling and make NROM cell has chance from multi time programming become true flash.