標題: 一個20Gb/s, 積分型整合鮑率時脈與資料回復電路之光接收機
A 20Gb/s Integrating Type Optical Receiver with Baud-Rate Clock and Data Recovery Circuit
作者: 李元勝
陳巍仁
Lee, Yuan-Sheng
Chen, Wei-Zen
電子研究所
關鍵字: 光接收機;時脈與資料回復電路;Optical receiver;Clock and data recovery circuit
公開日期: 2017
摘要: 本論文提出一個操作在 20Gb/s的光接收機,利用積分取樣式的類比前端接收電路,用以取代傳統高功耗的信號放大器電路,同時整合了鮑率式時脈與資料回復電路,減少了正交相位時脈訊號的使用,大幅減少時脈產生器所需要的功率消耗以及面積,預期可以應用於短距離高密度之光連結系統,如 Optical HDMI、資料中心等高資料頻寬之平台。本晶片使用台積電 40-nm bulk CMOS製程,在資料頻寬 20 Gb/s 以及誤碼率 (BER) 小於10-12時,可達到能量效益 2.4 pJ/bit,靈敏度 -10 dBm,核心電路面積為 0.09mm2。
This thesis describes a 20Gbps optical receiver. Integrating type front-end is exploited to replace the conventional power-hungry linear amplifier. Also, it is highly integrated with baud-rate CDR which can reduce power dissipation and hardware complexity of clock distribution network by half. This chip is fabricated in tsmc 40-nm bulk CMOS and achieves an energy efficiency of 2.4 pJ/bit. For bit error rate of less than 10-12, the input sensitivity is -10 dBm. The core circuit area is 0.09 mm2
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070250247
http://hdl.handle.net/11536/141469
顯示於類別:畢業論文