标题: 应用于次世代定序之高速资料处理器设计与实现
Design and Implementation of a High-Speed Data Processor for Next-Generation Sequencing
作者: 吴易忠
杨家骧
Wu, Yi-Chung
Yang, Chia-Hsiang
电子工程学系 电子研究所
关键字: 次世代定序;快速排序演算法;字串搜寻;基因定序;桶排序;Next-generation sequencing;fast serial sorting algorithm;string matching;DNA sequencing;Bucket sorting
公开日期: 2016
摘要: 近年来生物领域对于基因的各项研究都越发重要,而能够快速的搜寻出任意DNA片段位址对于不管是在生物或医学研究领域都有非常大的助益。基因定序是将DNA内部含氮硷基(由四种嘌呤与嘧啶所构成) 的确切位置标的出来的技术。人类的基因拥有大约三十亿个含氮硷基,要彻底地在如此巨大的序列之中搜寻出某个特定片段是非常耗时的。多方的研究也因此使现今的高通量定序技术(亦称为Next-Generation Sequencing、次世代定序)与发展越来越成。一般来说,要在如此大量的资料内搜寻出
某个特定片段,我们需要先将其排序,并且记录所有片段的前缀代号(suffix)并搭配进一步的搜寻与分析。而过长的排序时间是整个次世代定序分析的主要挑战与瓶颈。本论文提出一个具有高效率的次世代基因定序分析之硬体设计方法。其中亦使用了BWT与FM-indexing 演算法来呈现搜寻基因片段的功能。此论文提出藉由桶排序(Bucket sort)、分群与硬体快速排序电路大量降低硬体复杂度。为了达到最佳的硬体成本与执行时间的平衡,许多重要参数都必须详细与严谨的分析来达到最佳效能。
此NGS 资料处理器是由台积电四十奈米制程所下线,其可达到相较于软体演算法有147 倍的加速效果,同时相较于高效能GPU 亦有12 倍的以上的效率提升。
There is a strong scientific and medical need for a mechanism by which to search for arbitrary sequences in DNA. DNA sequencing is the process of determining the precise order of nucleotides (i.e., adenine, guanine, cytosine, and thymine) within DNA. Human DNA contains about three billion nucleotides, thus searching the entire genome for a specific sequence is very time consuming. This has driven the development of high-throughput sequencing, also known as next-generation sequencing (NGS). Generally, to search for an
arbitrary sequence from among a large volume of DNA nucleotides, all sequences should be pre-sorted and each suffix array is recorded. The high computational complexity in the pre-processing stage still poses design challenges. This work proposes a design methodology
associated with efficient hardware mapping for NGS with suffix array sorting and sequence searching. The Burrows-Wheeler Transform (BWT) with the Ferragina-Manzini (FM) index is used to improve storage capacity. Hardware complexity is significantly reduced through distributed sorting, grouping, and fast serial sorting circuits. Key design parameters are analyzed to achieve optimal performance, thus balancing hardware cost and execution time. Designed using 40nm CMOS technology, the proposed NGS sorting processor achieves a 147x speedup compared to the software algorithm and a 12x speedup compared to the high-end GPU implementation.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070250228
http://hdl.handle.net/11536/141584
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