感測整合電路模擬與量測差異補償之佈局技術

Abstract

本論文提出了電路佈局結構設計，調整了感測器與讀出電路。介紹製程演進所引起的效應問題，擴散區長度效應、氧化物間距效應、鄰近效應、IR drop，在模擬感測器暨整合電路單晶片設計時，目前的EDA軟體尚未有準確模擬各種CMOS製程效應，因此在模擬和測量之間存在一定的差距。所以提出了補償模擬方式和提升效能。藉由分析電流變化和減少效應對電路造成的影響，調整佈局繞線和設計電路的對稱性來得到最佳的佈局架構，並且比較不同的佈局方式。利用聯電0.18微米標準CMOS製程的金屬線電流公式來換算電路每條線路所需要的寬度值，最後透過模擬IR drop分析各條線路所能承受的電流值。 本論文將著重於設計的佈局技術，以補償模擬和測量的差異。根據模擬結果，提供給電路的電源繞線提高了約50%的電流值，整體面積縮減了約30%，諧振頻率的測量結果約為42kHz。

This thesis presents a circuit layout design and modification of the sensor and readout circuit. Introduce the effect of the process, the length of the diffusion effect, the oxide spacing effect, the well proximity effect, and the IR drop effect. The EDA software has not yet accurately simulated a variety of CMOS process effects, so there is a gap between simulation and measurement, and proposed compensation model and the efficiency. In the layout circuit design using solid structure symmetry, by analyzing the effects of current changes and reduction effects on the circuit, adjust the layout winding and design the symmetry of the circuit to get the best layout architecture, and compare the different layout methods to simulate the best results for the circuit. Using the metal line current of the UMC 0.18μm technology formula to calculate the width of each line required circuit value, and finally through the simulation IR drop analysis of the lines can withstand the current value. According to the simulation results, the power supply routing provided to the circuit was modified to increase the current value by 50%, and the overall area was reduced by about 30%. the resonant frequency measurement result is about 42kHz.