多核心Java處理器的優先權執行緒排程電路設計

Abstract

本論文主要目的是改進之前實驗室所開發的JAIP應用處理器核心，以設計一個不需依靠RISC處理器就能自行啟動系統的四核心Java處理器。並進一步針對Thread Manager進行修改，拆成Two-level的Thread Manager，也將原本設計的Data Coherence Controller修改為Multicore Coordination Controller，並將Global 的Thread Manager 新增至Multicore Coordination Controller之中的Inter-core Thread Manager，同時也將Thread Control Block list(TCB list)從local的Thread Manager移動到Inter-core Thread Manager。另外新增了設定優先權的機制，在local Thread Manager新增了有優先權的排程器。另外也做了一些coding style的修改，縮減電路的資源使用量。

We implement a quad-core Java Application IP(JAIP-MP) with multi-level priority scheduler in this thesis and integrate Power-on Bootup Logic(POBL) into JAIP-MP SoC to bootup system. We propose a two-level hardware scheduler which is global and local. Inter-core Thread Manager in Multi-core Coordination Controller(MCC) can be see as a Global Scheduler which is responsible for distributing a thread to one of the cores. In addition, we move Thread Controller Block list(TCB list) from JAIP core into MCC. In local scheduler, we replace single-level round-robin hardware scheduler into multi-level priority queue scheduler.