標題: | Temporal Multithreading Architecture Design for a Java Processor |
作者: | Su, Hung-Cheng Wu, Tsung-Han Tsai, Chun-Jen 資訊工程學系 Department of Computer Science |
關鍵字: | JAVA PROCESSOR;TEMPORAL MULTITHREADING;EMBEDDED SYSTEMS |
公開日期: | 1-一月-2014 |
摘要: | In this paper, we presents the design of a hardware temporal multi-threading architecture for a Java processor. The Java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the Java stack If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the Java runtime stacks for context switching would be expensive operations. We propose a Ping-Pong buffer architecture in this paper to facilitate fully hardware-based multi-threading capability for a Java processor. The proposed hardware architecture has been implemented and verified on an FPGA platform, Xilinx ML605. The experimental results show that the proposed context-switching efficiency is much higher than that of a software-based VM such as the CVM-JIT. Therefore, the proposed hardwired Java processor is promising for embedded applications that require heavy multi-threading operations. |
URI: | http://hdl.handle.net/11536/124907 |
ISBN: | 978-1-4799-3432-4 |
ISSN: | 0271-4302 |
期刊: | 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 2201 |
結束頁: | 2204 |
顯示於類別: | 會議論文 |