考慮先進製程下同時多重導線之時序導向繞線層分配

Abstract

在晶片的運作中，有正確的時序才能確保運作時資料同步的正確性，因此在不同的設計階段中，優化時序的表現一直是個重要的議題。先進製程中的電阻電容效應造成在低層的連線電阻值可能是高層導線電阻值的二十幾倍。而較小的電阻值可以得到較小的延遲時間，犧牲線長繞路使用高層的導線也有可能得到較佳的延遲時間。先前的研究沒有將電阻電容效應考慮進來，傳統的繞線層分配 (Layer Assignment)透過最小化線長和上下層金屬通路 (via)的數量，來得到較短的路徑以優化延遲，然而在電阻電容效應之下，並不是最小化路徑就能減少延遲時間，此外先前的研究較少針對多個net同時考慮，如果每次只針對單一個net做層分配，會衍生出net的排序先後的問題。而先前考慮電阻電容效應下的漸進式 (incremental)繞線層分配研究當中，只在選定的net之中做繞線層交換，如果是在繞線較擁擠的地區，會有導線資源不足無法交換的問題，另外因為前人將每個gcell獨立處理，gcell的邊界處可能會發生線段 (segment)無法銜接的問題。為了克服這些挑戰，本論文中提出多重導線之時序導向繞線層分配的平台，一開始為了讓每個gcell中可以拿來交換的繞線層資源充足，會對部分的net做重新繞線，再來我們使用雙邊最大匹配的演算法對gcell中的線段重新分配，最後針對低層的線段，在可使用的限度之下增加附屬平行導線 (parallel wire)以降低電阻值。實驗結果顯示，我們的平台可以有效改善時序的表現。

Timing optimization is essential for IC design; only correct timing can ensure correct data synchronization. At advanced technology nodes, RC effect makes the metal resistance on lower layers more than twenty times bigger than those on higher layers. Using the metal on higher layers increases wire length and vias, but might result in less delay due to less resistance. Traditional layer assignment minimizes total wire length and via count to optimize delay without considering RC effect. However, wire length and via count minimization cannot guarantee delay minimization under RC effect. In addition, no much work handles layer assignment for multiple nets in one time. Considering a single net at a time causes the net ordering issue. Recent incremental layer assignment works reassign layers among critical and non-critical nets. However, in routing congestion areas, the lack of resource for layer exchange limits delay improvement. Besides, they deal with layer assignment in each partition separately thus possibly causing the disconnection between segments on gcell boundaries. Therefore, we propose a framework for concurrent timing-driven layer assignment for multiple nets. We refine partial net topology to enrich the layer resource in the beginning. Then we perform Bipartite Matching to reassign segments to layers in gcells. At last, we apply parallel wires to reduce wire resistance on lower layers. Our results show that our framework can improve timing performance effectively.