寫入/抹除 偏壓與氧化製程在快閃記憶體之可靠度研究

Abstract

此篇論文針對使用ＴＥＧ結構之快閃記憶體在不同寫入／抹除電壓以及不同氧化製程之間之耐久度之研究． 穿隧氧化層之劣化被認為是目前快閃記憶體可靠度最重要的研究議題，透過特殊結構（TEG STRUCTURE）可以將浮動閘極內的電荷以及穿隧氧化層內因氧化層老化而被陷阱抓住之氧化層電荷分離，進而分析穿隧氧化層老化之物理機制． 在前一篇論文中，提出了＂電子陷阱被捕之截面積（σ）＂，陷阱狀態能階（Etrap），在寫入／抹除次數小於１００次時，可解釋量測到之物理現象，然而，在寫入／抹除次數大於１００次後尚無法找到與實驗數據相符合之物理模型． 本篇論文提出＂隨著寫入／抹除次數所產生之新能階＂之一種可能模型來解釋本實驗室量測到的數據，並成功在寫入／抹除次數為１０００次與３０００次時成功解釋量測現象．此模型同時也可解釋濕氧化與乾氧化製程，並將量測與模擬數據呈現於本篇論文中．

In order to understand the degradation mechanism in the tunnel oxide of NAND Flash memory cell, TEG structure is used, instead of conventional NAND Flash memory cell.In previous study, the endurance characteristic was analyzed. Electron trapping and de-trapping was analyzed during P/E operation. Trapping process mainly occurs after the P/E electrons tunneling through the oxide barriers. Thus, the number of trapped electrons depends on the position in the oxide. On the other hand, the trapped electrons are also de-trapped from the trap states. Thus, trapping and de-trapping process must be simultaneous calculated.By using generation rate = 10-7, the simulation result can explain three different bias (13V, 15V, 17V) under dry oxidation. The simulation also shows that using same generation rate can fit the experimental data between dry and plasma oxidation.