标题: 复合高介电系數闸极介电层在三五族半导体中之缺陷特性及其可靠度研究
A Study of Trap Characteristics and Reliability in Ⅲ-V Compound Semiconductor with Stacking High-k Gate Dielectrics
作者: 曲崇铭
李威仪
Chu, Chung-Ming
Lee, Wei-I
电子物理系所
关键字: 氮化镓;砷化镓;复合高介电系數介电层;金氧半;可靠度;依时性介电崩溃;缺陷;GaN;GaAs;Stacking High K Dielectrics;MOS;MIS;Reliability;TDDB;Trap
公开日期: 2017
摘要: 由于一般三五族半导体,氮化镓、砷化镓,缺乏自然生成的高品质氧化层,不若矽半导体有很好的高品质氧化矽,因此借助高介电系數介电层当做高闸极介电层是有需要的。然而三五族半导体与高介电系數介电层属不同材质成长,由于异质结合及晶格不匹配,因此在表层含有大量缺陷。这对于高介电系數介电层不管应用在在金氧半电晶体当做高闸极介电层,或应用在金属-绝缘体-半导体的闸极结构高电子迁移率电晶体当做漏电阻挡层,皆会对元件特性产生极大的冲击。因此本论文先以结构简单的金氧半电容元件研究堆叠式氧化层结构高介电系數介电层的可靠度,施予垂直电场电性应力,以检测在垂直电场电性应力作用下,研究缺陷形成机制及介电层寿命。矽半导体的可靠度分析方法皆可应用在化合物半导体。接下来扩展到三端的元件,堆叠式氧化层结构来制作金属绝缘层氮化镓高电子迁移率电晶体,同时施予水平及垂直电场电性应力,以检测在水平及垂直电场电性应力作用下,研究缺陷如何影响元件特性及寿命。第三部份藉由三端的元件失效的机制,进一步研究堆叠式氧化层结构来制作金属绝缘层氮化镓电容元件,闸极绝缘层可靠度寿命。电流传导机制的衰退及介面缺陷的变化皆予以探讨。
Lacking high quality natural oxide films would be a problem for those devices built by III-V compound semiconductor, such as GaAs and GaN, They don’t have natural oxide films, such as SiO2 for Silicon, to form gate oxide film. It’s necessary to look for high-κ dielectric film as replacement. But the interface exist lots of traps between semiconductor and high-κ dielectric film due to lattice mismatching from hetero-epitaxial structure. This problem will impact the device performance for MOSFET which uses high-κ film as gate oxide, or MIS-HEMT ( metal insulator semiconductor high electron mobility transistors ) which uses high-κ film to improve gate leakage. This thesis studies the reliability, finds the failure mechanism, and evaluates the lifetime on stacking high-κ dielectric design in III-V compound devices. The first portion starts on simple MOS capacitor structure with stacking high-κ films to investigate the time-dependent dielectric breakdown (TDDB) characteristics and trapping mechanism by applying vertical voltage stress. Silicon based reliability analysis method could be as a reference to be applied on compound semiconductor, The second portion extends to 3 terminals MIS-HEMTs to evaluate the lifetime and trapping effect by applying both vertical and horizontal voltage stress. The third portion further studies MIS capacitor with stacking high-κ films based on failure mode in the second portion. Degradation on current transportation mechanism and interface traps density (Dit) will be discussed.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070082007
http://hdl.handle.net/11536/142181
显示于类别:Thesis