利用FPGA實現GPSR演算法則

Abstract

先前實驗室學長官靖喬以FPGA-ARM的嵌入式系統完成一套GPS接收機且能順利解調訊號。本研究希望能在既有的基礎上持續改善演算法，以提高定位精度與性能。

GPS演算法的改善／修正極其困難，主要原因如下：（1）演算法的輸入訊號（衛星訊號）的訊噪比低，且隨著射頻前端（RF frontend）晶片性能不同而異，因此錯誤的重現性差。（2）GPS接收機的實現平台為一嵌入式系統，其包含即時作業系統與FPGA／ARM兩種硬體架構與程式語言，訊號的傳遞與時脈的掌控較為複雜，且取樣／數位化的過程亦會造成訊號的失真。（3）GPS訊號的解調過程是一個即時（real-time）的迴授系統，當錯誤發生時，很難確定出錯的模組。本研究提出數種作法來建立GPS訊號處理的除錯環境，並以此除錯環境進行GPS接收機演算法的改善。改善內容包括：使用pipeline技術增加系統強健性、使用「同步器（synchronizer）」解決「跨時脈變換（CDC, Clock Domain Crossing）」的問題、增加相位解調之解析度、使用I/Q頻道訊號增加訊號的訊噪比、改善鎖相迴路以符合高動態需求等。

目前研究結果顯示改善後之GPSR演算法的強健性優於原先版本，且可以在不同的FPGA平台上正確運行。其它性能的改善都如預期，並且在所建立的除錯環境下完成驗證。

Previously, our research group developed a global position system receiver (GPSR) and implemented it on a platform consisting of both FPGA and ARM. The aim of this thesis is to continue on the improvement of the previous work, specifically for the robustness of the GPSR algorithm and positioning accuracy under high dynamics measurements.

To improve the performance of the GPSR is a challenging work for the following reasons. Firstly, the input signal to the GPSR is the radio-frequency (RF) signal from satellites and processed by the RF frontend. Both the low signal-to-noise ratio (SNR) of the satellite signal and the performance variation of the RF frontend make the input signal unreliable. Thus, the error signals of the GPSR are irreproducible. Secondly, the GPSR algorithms are implemented on an embedded system consisting of both ARM and FPGA. ARM and FPGA use different approaches and different programming languages to realize algorithms. Besides, the communication between ARM and FPGA, the discretization/ digitization of a RF signal, and etc all introduce considerable amount of errors to the system. Thirdly, the demodulation of the GPSR signal is a real-time, feedback process. It is difficult to identify errors from numerous modules. This work solves these problems by providing GPS test signals and by developing several debugging tools for the FPGA-ARM platform. With the assistance from such, we make several changes to the previous algorithms which include: introducing pipelines techniques to the algorithm, using "synchronizer" to solve the clock-domain-crossing (CDC) problem, increasing the resolution of the phase accuracy, using both in-phase and quadrature-phase signals to improve the SNR of the input signal, modifying the phase lock loop (PLL) design, and etc.

The experimental results indicate the new algorithm is much more robust than the previous one, and can work on different FPGA platforms. Other performance improvement are all discussed in detail and verified by the proposed debugging tools.