RFID整流器與低雜訊放大器

Abstract

本篇論文針對以下兩個獨立的電路進行研究：35 GHz低雜訊放大器以及 5.8 GHz RFID整流器。低雜訊放大器對於任何一個接收器架構來說都是重點電路，而在設計過程中有許多的效能需要被考慮 (例如：noise figure、增益、線性度以及IP3等等), 為了達到我們的設計需求，本篇論文所提出的低雜訊放大器使用了三級的電感簡併低雜訊放大器結構，其使用了砷化鎵 0.15 m pHEMT製程，並且在35 GHz的操作頻率下達到17 dB的增益以及2.6 dB的noise figure。 低功率整流器在如RFID或生醫領域等應用中，負責供應整個系統電源，其在系統中扮演了一個關鍵的角色。在整流器的設計上，電晶體的臨界電壓、逆向漏電電流、輸入電壓甩幅為主要的設計瓶頸，而為了克服這些限制，我們使用了此論文所提出的整流器架構。此篇論文所提出的整流器使用了TSMC 65奈米製程，並且針對260mV的電壓達到了-25 dBm的敏感度。除此之外，擁有5.8GHz LTCC製成匹配架構的橋式整流器也在此篇論文中被提及。

This thesis investigates two types of works: Low Noise Amplifier at 35GHz and RFID Rectifier at 5.8GHz. Low noise amplifier (LNA) is the main module in any receiver architecture. There are several properties (i.e., noise figure, gain, linearity and low IP3 and so on) to be investigated in LNA design. To meet our requirements, 3-stage Millimeter Wave Inductor Degenerated low noise amplifier was designed in GaAs - 0.15um pHEMT technology to achieve the 17dB gain and 2.6dB noise figure at the 35GHz frequency. The ultra-low power Rectifier plays a vital role to supply the power in many applications such as RFID, Bio-medical and so on. In any rectifier design, most dominant eventual issues are threshold voltage of MOSFET, reverse leakage current and input voltage swing. To overcome these constraints, Adapted In-phase gate boosting rectifier (AIGR) was implemented. In this method, 30 stage rectifier was designed by using TSMC 65nm technology to achieve the higher sensitivity about 260mv at -25dBm RF input power. Moreover, a separate 5.8GHz LTCC based bridge type rectifier with new matching approach was discussed.