應用於900–1800MHz GSM規格的高功率CMOS T/R開關之靜電放電防護設計

Abstract

近年來，隨著矽製程的演進，射頻積體電路 (radio-frequency integrated circuits, RFICs)已經可以在一般的CMOS製程中實現，如此以來，不但可以降低製造成本，也可以提升與其他射頻電路區塊的整合性。而隨著電晶體尺寸微縮，雖然達到了提升邏輯閘的運算速度以及降低電源功率消耗的目的，但來自靜電放電 (electrostatic discharge, ESD) 的威脅，卻不會因為製程的先進而降低，因此靜電放電防護設計是在積體電路的可靠度中是一個不可忽略的問題。在射頻積體電路中，靜電放電防護設計除了要能夠達到一定的工業規格之外，也不能影響到射頻電路中敏感的射頻效能參數及正常的電路操作。因此，必須以非常嚴格的標準來設計ESD防護元件以期將其所帶來的寄生效應對高速射頻訊號的影響降至最低。 本論文分為兩大部分，第一部分為針對應用於手機通訊中的高功率T/R 開關(transmit/receive switch, T/R switch) 電路架構所設計的ESD 靜電放電設計。在高功率T/R 開關的堆疊 (multi-stacked) 架構中，由於射頻訊號大振幅與高頻率，會使得一般傳統的靜電放電防護設計將正常的射頻訊號誤判為靜電，將正常的射頻訊號排放到地而造成失真。本論文所提出新的靜電放電防護設計並不使用額外的電流疏通路徑，而是利用辨識射頻訊號和ESD 的行為差異，可以在靜電來臨時開啟自身電晶體的方式來將電流導入到地。此設計已在0.18微米CMOS製程中實現，相較於未加入靜電放電防護設計的原始電路，能夠達到良好的靜電防護效果。ESD的耐受度及T/R開關射頻電路的參數特性將在論文中完整的討論。 第二部分為應用在典型T/R開關中的靜電放電防護元件，利用原本就存在於傳統靜電放電防護電路之中的二極體 (diode) 以及金氧半電晶體 (MOS transistor) 之間的寄生路徑，透過電路佈局技巧組合出一個嵌入式矽控整流器 (embedded silicon-controlled rectifier) 並實現於90奈米CMOS製程中。此外，藉由電源與地之間的靜電放電箝制電路 (power-rail ESD clamp circuit) 的偵測電路提供觸發訊號將嵌入式矽控整流器在靜電來臨時開啟，成功地降低導通電阻 (Ron) 並提高T/R switch對PS-mode ESD的耐受度。

In recent years, radio-frequency integrated circuits (RFICs) have been successfully implemented in CMOS process thanks to the fast development of CMOS technologies. In this way, the RFICs can be integrated in a system on chip (SOC) for mass production with lower cost of IC manufacturing. As the transistors scale down rapidly, the oxide thickness becomes thinner and provide faster logic operations with lower energy consumption. However, the threat from electrostatic discharge (ESD) phenomenon was not alleviated as technology advances. In RFICs, the ESD protection circuit must provide enough ESD robustness without disturbing the normal circuit operations. Thus, the ESD protection design must be strictly conducted in order to minimize the parasitic effect of the ESD devices lest it should degrade the performance of the high-speed RF signal. There are two major parts in this thesis. The first part of the thesis targets on the T/R switch which is applied for cellular device. In a high-power T/R switch, traditional ESD protection method cannot be used since the large amplitude and high frequency of the RF signal will mis-trigger the traditional ESD protection design. As a consequence, in this work, there is no additional discharging path employed to discharge the ESD current. Instead, by identifying the behavior of the ESD transients and the normal RF signal, the transistors in the proposed ESD protection design can trigger the inherent transistors of the T/R switch in the PS-mode zapping event and discharge the ESD current. The proposed ESD protection design for high-power T/R switch has been fabricated in a 0.18-µm CMOS process and achieved good ESD levels. RF performance and ESD characteristics are measured and analyzed in the thesis. The second part focuses on an ESD protection device for typical T/R switch applications. By using the diodes and MOS transistors which are already designed in the T/R switch with conventional ESD protection, embedded silicon-controlled rectifiers (embedded SCR) are implemented in a 90-nm CMOS process by layout skill. The proposed ESD protection with embedded SCRs and power-rail ESD clamp triggered can enhance the PS-mode ESD robustness of the T/R switch successfully.