奈米級鰭狀場效電晶體之金屬閘極顆粒度製程變異及隨機擾動訊號引致臨界電壓偏移模擬分析

Abstract

在現今的半導體元件製程當中，製程變異是一個相當重要的議題。製程變異所影響的特性當中，臨界電壓的隨機變異分布尤為重要。在這篇論文裡，我們使用三維電腦科技輔助軟體Sentaurus ，針對Intel 發表的 14奈米製程的鰭狀場效電晶體作為校準目標建立模擬元件。我們採用氮化鈦作為金屬閘極材料，以金屬閘極顆粒度為製程變異的主要來源，模擬臨界電壓的隨機分布狀況。同時我們也探討不同金屬顆粒大小的影響。此外，在考慮元件金屬閘極顆粒度製程變異的情況下，我們加入由氧化層介面陷入電荷，引起隨機擾動訊號並產生臨界電壓偏移。我們發現隨著元件尺寸微縮，隨機擾動訊號引起的最大臨界電壓偏移與製程變異的關聯性會上升，並且在縮小元件尺寸和金屬顆粒大小的情況下，隨機擾動訊號對臨界電壓的影響會逐漸增強，可以與製程變異匹敵。此外，我們還模擬了由於偏壓溫度不穩定性，而產生的多數氧化層陷入電荷所引致的臨界電壓隨機分布，分析在不同元件尺寸和金屬顆粒大小下，其對於陷入電荷密度的關系和趨勢。此研究中，我們藉由機率統計分布的模擬，提供元件設計的一個參考。

In current semiconductor device process, the process variability is a crucial issue. For all characteristics associated with process variation, random variation of threshold voltage is especially important. In this thesis, with the help of commercial 3D technology computer-aided design (TCAD) Sentaurus, we build up our simulation structure calibrated with respect to Intel published 14-nm technology node FinFET device. TiN is chosen to be the metal gate material. We assume metal gate granularity (MGG) as the main source of process variation to simulate the distribution of threshold voltage variation. Meanwhile, we also discuss the effect of different average grain size (AGS). Furthermore, with the consideration of MGG, we add an oxide charged trap at the interface to induce random telegraph noise (RTN), and consequently cause threshold voltage shift (ΔVth). We find that with the device scaling, the correlation between maximum RTN ΔVth and process variation grows stronger. Besides, the impact of RTN becomes significant enough to compete with the process variation as device shrinks and AGS decreases. In addition, we perform simulations on ΔVth variation due to multiple traps induced by BTI stressing. We analyze the relation between it and trap density under conditions of different device scales and AGS. Through this statistical simulation work, we provide a reference for device designing.