管狀通道無接面多晶矽電晶體之製作與特性研究

Abstract

在本篇論文中，僅藉由 I-Line 微影技術成功製作出高度微縮之具有管狀通道的無接面多晶矽電晶體。透過氧化矽側壁硬式光罩(oxide-spacer hard mask)，管狀通道的介電質奈米線核(core)的寬度可微縮至30奈米以下。本文並透過同步摻雜之低壓化學氣相沉積技巧，形成多晶矽無接面電晶體之高摻雜濃度之通道。由實驗所得低於 120 mV/dec 的次臨界擺幅以及可忽略的汲極引發勢壘降低，證實結合超薄通道(ultra-thin body)與環繞式閘極(gate-all-around)的元件所展現的良好閘極控制能力。論文中也討論管狀通道無接面多晶矽電晶體的漏電流來源及產生機制，亦分析使用兩種不同介電質材料作為核心的元件之基本電性的差異，以及與通道長度相關的特性變化。

In this thesis, a novel scheme for fabricating the JL poly-silicon transistors with horizontal macaroni-channels wrapping a dielectric core (oxide or nitride) is proposed and demonstrated. In this scheme, I-Line-based lithography was employed to generating the patterns. By means of oxide-spacer hard mask, the dimensions of the macaroni-channel can be effectively scaled to an extent smaller than 30 nm. The highly doped poly-Si macaroni was deposited by LPCVD with in-situ doping. The utilization of ultra-thin channel and of the GAA configuration allows the fabricated devices to exhibit good electrical characteristics in terms of small S.S. and negligible DIBL evidencing the good gate controllability. The dependences of channel length on device characteristics are also analyzed. We also explore the conduction mechanisms for the leakage current.