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dc.contributor.author翁偉倫zh_TW
dc.contributor.author闕河鳴zh_TW
dc.contributor.authorWeng, Wei-Lunen_US
dc.contributor.authorChiueh, Hermingen_US
dc.date.accessioned2018-01-24T07:42:49Z-
dc.date.available2018-01-24T07:42:49Z-
dc.date.issued2017en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350727en_US
dc.identifier.urihttp://hdl.handle.net/11536/142944-
dc.description.abstract隨著 VLSI技術的演進,類比電路已經被實現在更低提供壓及小晶 技術的演進,類比電路已經被實現在更低提供壓及小晶 片面積。 三角積分 類比 數位 轉換器 藉由過取樣 (oversampling)與雜訊移頻 與雜訊移頻 (noise-shaping)的方式 ,能夠輕易達到高解析度 能夠輕易達到高解析度 。 本論文 經由台積電的 0.18微米 設計與 製程 實現 一二階 三角積分 調變 器。在輸 入開關 上採用拔靴式並用最佳化過的單級正回授放大器來減低功耗 ,所設 計之 三角積分類比數位轉換調變器 經模擬後 的訊號雜比為 97dB、1V 供電壓 下功耗為 26uW,晶片總面積 晶片總面積 0.86x0.86 mm2(含 I/O pad)。zh_TW
dc.description.abstractWith the scaling down of VLSI technology, analog circuits are implemented under lower power supply and smaller chip area. Delta-Sigma modulator is able to achieve high resolution with oversampling and noise-shaping techniques. This work presents the design and implementation of a second order delta-sigma modulator with TSMC 0.18 um process. The input switches are bootstrapped switches and a optimized single-stage operational transconductance amplifier (OTA) with positive feedback is used to minimize power consumption. The post-layout simulation shows that the modulator is able to achieve a SNR of 97 dB with 26 uW power consumption under 1 V power supply. Chip area is 0.86x0.86mm2.en_US
dc.language.isoen_USen_US
dc.subject三角積分調變器zh_TW
dc.subject拔靴式開關zh_TW
dc.subject電容式切換電路zh_TW
dc.subjectdelta-sigma modulatoren_US
dc.subjectbootstrapped switchen_US
dc.subjectswitch capacitor circuiten_US
dc.title26uW、頻寬1KHz二階三角積分調變器之設計與實現zh_TW
dc.titleDesign and Implementation of a 26uW Second-Order Delta-Sigma Modulator with 1KHz Bandwidthen_US
dc.typeThesisen_US
dc.contributor.department電機工程學系zh_TW
Appears in Collections:Thesis