以共用開關之功率級架構 實現Σ－Δ調變D類音頻放大器

Abstract

本論文以Sigma-Delta Modulation為基礎設計D類音頻放大器。相較於類比式的A類、B類、AB類放大器，D類放大器有高效率、體積小、容易設計等優勢。有別於傳統D類放大器所使用的全橋式功率級，本論文所採用的共用開關之功率級架構，更可節省D類放大器的體積與成本。常見的D類放大器會以Pulse-Width Modulator或是Sigma-Delta Modulator來產生開關切換訊號。Pulse-Width Modulator架構簡單，然而固定的切換頻率使其有倍頻雜訊的問題。Sigma-Delta Modulator架構雖然較為複雜，但沒有倍頻雜訊的問題，並且在開關切換次數上也比Pulse-Width Modulator來得少，因此能獲得更高的效率。本論文將於FPGA實現穩定的Sigma-Delta Modulator DAC，並配合德州儀器的 介面IC 與共用開關之功率級，實現一D類音頻放大器。

This thesis aims at designing Class-D Amplifiers based on the method of Sigma-Delta Modulation. In contrast to Class-A, Class-B, and Class-AB Amplifiers, which use analog designs for circuits, Class-D Amplifiers have the advantages of being highly efficient, smaller in size, and simple to design. Unlike the Full-Bridge Power Stage often found in traditional Class-D Amplifiers, the application of Shared Switch Architecture Power Stage adopted in this thesis helps minimize the size of Class-D Amplifiers while reducing the producing costs. Common Class-D Amplifiers use either the Pulse-Width Modulator or the Sigma-Delta Modulator to generate switching command. The structure of the Pulse-Width Modulator is quite simple, but the fixed switching frequency causes the problem of harmonic distortion. Although the Sigma-Delta Modulator is more complex when it comes to structure, it does not have the problem of harmonic distortion, and compared to the Pulse-Width Modulator, it requires fewer times on the switching process, therefore making it possible to secure higher efficiency. This thesis aims to accomplish the designing and making of a Class-D Amplifier that not only ensures the stability of the Sigma-Delta Modulator DAC employed in FPGAs, but also features the utilization of the Texas Instruments Interface IC and Shared Switch Architecture.