標題: | A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata |
作者: | Tsai, Hsiang-Jen Chen, Chien-Chih Peng, Yin-Chi Tsao, Ya-Han Chiang, Yen-Ning Zhao, Wei-Cheng Chang, Meng-Fan Chen, Tien-Fu 資訊工程學系 Department of Computer Science |
關鍵字: | Deep packet inspection (DPI);discrete finite automata (discrete-FA);network security;simultaneous pattern matching;ternary content addressable memory (TCAM) based search engine;wildcard pattern matching |
公開日期: | 1-十二月-2017 |
摘要: | Regular expression matching becomes indispensable elements of Internet of Things network security. However, traditional ternary content addressable memory (TCAM) search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This paper proposes a promising simultaneous pattern matching methodology for wildcard patterns by two separated engines to represent discrete finite automata. A key preprocessing to encode possible postfix pattern by a unique key ensures that follow-up patterns can accurately traverse all possible matches with limited hardware resources. This approach is practical and scalable for achieving good performance and low space consumption in network security, and it can be applicable to any regular expressions even with multiwildcard patterns. The experimental results demonstrate that this scheme can efficiently and accurately recognize wildcard patterns by simultaneously tracking only two active states. By adopting SRAM TCAM in the proposed architecture, the energy consumption is reduced to around 39%, compared with the energy consumption using a computing system that contains a large memory lookup and comparison overhead. |
URI: | http://dx.doi.org/10.1109/TVLSI.2017.2671408 http://hdl.handle.net/11536/144158 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2017.2671408 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 25 |
起始頁: | 3302 |
結束頁: | 3316 |
顯示於類別: | 期刊論文 |