Asymmetry dual-LFSR reseeding for low power BIST

Abstract

Growing test data volume and excessive test power consumption are two of the major concerns for the industry when testing large integrated circuits. LFSR-decompressor-based compression methods have been widely adopted to reduce test data volume because they can provide high compression ratio. These techniques have been enhanced to address the need for low power as well as low test data volume. The key idea behind these methods is to generate seeds for LFSR reseeding such that the don't-cares in test cubes are filled with proper values to reduce the transition count. This paper presents a LFSR reseeding approach adopting dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Two LFSRs are used to jointly generate test patterns for a given test set to increase the correlation between neighboring bits and thus to reduce the transition count. Experimental results on the ISCAS'89 benchmarks demonstrate that our proposed approach can achieve a better compression ratio than the existing related dual-LFSR scheme while keeping a roughly equal shifting power reduction.