Bipolar Dual-LFSR Reseeding for Low-Power Testing

Abstract

Large test data volume and excessive test power are two strict challenges for VLSI circuit testing. Built-in self-test (BIST) is recognized as a good solution to the problem of large test data volume. LFSR-decompressor-based compression methods have been widely adopted in BIST to reduce test data volume. The effectiveness of this approach is on the ability to control the generated pseudorandom pattern. This paper adopts dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that it has a significant reduction of data volume and test power using the proposed new Bipolar Dual-LFSR reseeding approach as compared to the existing related dual-LFSR schemes.