標題: Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration
作者: Shen, Wen-Wei
Chang, Hsiao-Chun
Yang, Yu-Tao
Hu, Yu-Chen
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D heterogeneous integration;double-self-assembly technology
公開日期: 1-Feb-2018
摘要: Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of mu-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.
URI: http://dx.doi.org/10.1109/TCPMT.2017.2775861
http://hdl.handle.net/11536/144490
ISSN: 2156-3950
DOI: 10.1109/TCPMT.2017.2775861
期刊: IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
Volume: 8
起始頁: 310
結束頁: 316
Appears in Collections:Articles