完整後設資料紀錄
DC 欄位語言
dc.contributor.authorPanigrahy, Asisa Kumaren_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:53:26Z-
dc.date.available2018-08-21T05:53:26Z-
dc.date.issued2018-03-01en_US
dc.identifier.issn1043-7398en_US
dc.identifier.urihttp://dx.doi.org/10.1115/1.4038392en_US
dc.identifier.urihttp://hdl.handle.net/11536/144700-
dc.description.abstractArguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu-Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu-Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu-Cu bonding for 3D IC and heterogeneous integration applications.en_US
dc.language.isoen_USen_US
dc.titleLow Temperature Cu-Cu Bonding Technology in Three-Dimensional Integration: An Extensive Reviewen_US
dc.typeArticleen_US
dc.identifier.doi10.1115/1.4038392en_US
dc.identifier.journalJOURNAL OF ELECTRONIC PACKAGINGen_US
dc.citation.volume140en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000427846400002en_US
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