標題: Reducing Forming Voltage by Applying Bipolar Incremental Step Pulse Programming in a 1T1R Structure Resistance Random Access Memory
作者: Zheng, Hao-Xuan
Chang, Ting-Chang
Xue, Kan-Hao
Su, Yu-Ting
Wu, Cheng-Hsien
Shih, Chih-Cheng
Tseng, Yi-Ting
Chen, Wen-Chung
Huang, Wei-Chen
Chen, Chun-Kuei
Miao, Xiang-Shui
Sze, Simon M.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Resistance random access memory (RRAM);1T1R;incremental step pulse programming (ISPP);forming voltage
公開日期: 1-Jun-2018
摘要: This letter introduces a method of using bipolarity bias voltages in the forming process to effectively reduce the forming voltage of a one-transistor and one-resistance random access memory device. A bipolar incremental-step-pulse programming process is applied, and a complete operation pulse for the forming process is described. This method reduces forming voltage without any cost to the device performance, and the device maintains good reliability. The likely physical mechanism of this bipolar operation is also presented based on the measured electrical characteristics.
URI: http://dx.doi.org/10.1109/LED.2018.2831708
http://hdl.handle.net/11536/145203
ISSN: 0741-3106
DOI: 10.1109/LED.2018.2831708
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 39
起始頁: 815
結束頁: 818
Appears in Collections:Articles