二氧化鉿基底電阻式記憶體之動態轉換物理模型

Abstract

傳統非揮發性記憶體如FLASH和SONOS等載子陷阱式記憶體有著許多先天上的微縮限制，如隨機摻雜擾動（Random Dopant Fluctuation）、隨機電報雜訊（Random Telegraph Noise）和最小穿遂氧化層厚度。為了解決上述的問題，一種藉由電阻轉換的全新記憶體在近年來被廣泛地討論及研究。在所有電阻轉換記憶體當中，以過渡金屬氧化物作為介電基層的電阻式隨機存取記憶體（Resistive Random Access Memory）被最為看好，因為它製程與結構簡單，還有極佳的微縮性質，低電壓操作和多位元儲存的可能性。

已經有相當多的文獻討論不同電阻式記憶體介電層和電極材料的影響與特性，但是對於其電阻轉換機制卻缺乏完整的了解。截至目前雖有不少文獻針對電阻式記憶體電流電壓特性提出的模型，例如空間電荷限制電流（Space Charge Limited Current）、法蘭克－普爾傳輸（Frenkle-Poole Transport）、蕭基能障熱發射（Shottcky Barrier Thermal Emission）和離子的飄移擴散模型。這些模型往往只能解釋部份的電阻轉換現象，但在別的現象是失效的。本篇論文的研究目的在於建立一個既簡單明瞭又能完整解釋電阻式記憶體各種電阻轉換現象的模型，並且深入地了解電阻式記憶體特殊的遲滯電流電壓特性曲線。

由於電阻式記憶體的讀取電壓很小（約0.1V），介電層的厚度可以只有幾個奈米，而且其金屬－絕緣體－金屬的結構肯定會產生一個電流傳輸能障，這些因素皆滿足直接穿遂理論的條件。根據溫度變化實驗，我發現穿遂能障高度並不會跟著不同電阻值狀態而改變，因此關鍵必定在於穿遂能障的寬度。基於WKB近似法所作的模擬結果與實際量測數據相當吻合。模擬的結果顯示穿遂能障寬度與施加的重設電壓成正比關係，也就是說在電極與氧空缺（Oxygen Vacancy）構成的導電細絲尖端之間形成了一層不含電荷的介電層。阻態的開/關比例則受控於穿遂能障高度、電子等效質量和陷阱最大距離。我們也同時研究穿遂能障寬度的時變性質。我們發現在阻值轉換期間，穿遂能障寬度變化量與對數時間成線性關係，而轉換時間乃受控於電流大小、導電細絲的電荷密度和截面積的大小。

近年來的研究指出電阻式記憶體可能成為不曾被發現的第四種被動元件：憶阻器，由於憶阻器的電壓電流特性與電阻式記憶體相當類似。在本篇論文中我們提出一套系統化的數學方法並根據真實實驗數據來模擬電阻式記憶體的憶阻特性，以便將來應用在SPICE電路模擬程式之中。

Carrier-trapping memory devices (eg., FLASH, SONOS etc.) have several inherent scaling limits, such as random dopant fluctuation, random telegraph noise, and minimum tunnel oxide thickness. In order to solve the problems above, a new type of resistive-changing memory has been widely studied in recent years. Among all of the resistive-changing memories, the transition metal oxide based resistive random access memory (RRAM) is most prominent owing to its simple structure (Metal-Insulator-Metal, MIM) and fabrication, excellent potential of scaling, small voltage operation and possibility for multi-level storage.

Many papers with focus on RRAM dielectric and electrode materials have been published, but the switching mechanism of RRAM has not been well understood. So far, several models based on RRAM current-voltage characteristic have been published, for example, space-charge-limited current (SCLC), Frenkle-Poole transport, Schottky barrier thermionic emission, and Ionic drift & diffusion, etc. Each of them explains on some perspectives, but fails on other phenomena. The main purpose of my research is to construct a simple and well-explained model for RRAM switching mechanism and investigate the secret of RRAM special hysteresis current-voltage characteristic.

Since RRAM reading voltage is small (about 0.1V), the dielectric layer could be ultrathin (about few nanometers), and its MIM structure surely exhibits a barrier for transport electrons, it satisfies the constraints for direct tunneling. Based on temperature experiments, I found the tunnel barrier height is not changing for different resistance states, so the key must lie on the tunnel barrier width. The simulation based on WKB approximation successfully fits the real measurement data. The simulation shows that the tunnel barrier width is proportional to the reset voltage, which means there is a charge free dielectric layer formed between metal electrode and the tip of the conduction filament composed of oxygen vacancies. The resistance on/off ratio is controlled by barrier height, electron effective mass, and the maximum defect distance. The tunnel barrier width time varying property is also studied. During the transition, tunnel barrier width changes with logarithmic time. The switching time is controlled mainly by current amplitude, conduction filament charge density and cross section.

The possibility of RRAM as a long-missing forth passive element, memristor, has been widely discussed in more recent years. The memristor theoretical hysteresis current-voltage characteristic happens to be similar to the behavior of RRAM. We proposed a mathematical method to simulate RRAM memristive behavior in SPICE based on real transient measurement data.