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dc.contributor.authorYang, THen_US
dc.contributor.authorSu, CTen_US
dc.contributor.authorHsu, YRen_US
dc.date.accessioned2014-12-08T15:20:26Z-
dc.date.available2014-12-08T15:20:26Z-
dc.date.issued2000en_US
dc.identifier.issn0144-3577en_US
dc.identifier.urihttp://hdl.handle.net/11536/14531-
dc.description.abstractThis paper proposes to use Muther's systematic layout Planning Procedure as the infrastructure to solve a fab layout design problem. A multiple objective decision making;ng tool, analytic hierarchy process, is then proposed to evaluate the design alternatives. The proposed procedure is illustrated to be a viable approach for solving a fab layout design problem through a real-world case study. It features both the simplicity of the design Process and the objectivity of the multiple-criteria evaluation process as opposed to existing solution methodologies.en_US
dc.language.isoen_USen_US
dc.subjectlayouten_US
dc.subjectsemiconductorsen_US
dc.subjectmaterial handlingen_US
dc.subjectanalytical hierarchy processen_US
dc.subjectdecision makingen_US
dc.titleSystematic layout planning: a study on semiconductor wafer fabrication facilitiesen_US
dc.typeArticleen_US
dc.identifier.journalINTERNATIONAL JOURNAL OF OPERATIONS & PRODUCTION MANAGEMENTen_US
dc.citation.volume20en_US
dc.citation.issue11-12en_US
dc.citation.spage1360en_US
dc.citation.epage1372en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000165998000007-
dc.citation.woscount23-
Appears in Collections:Articles