標題: | A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter |
作者: | Chang, Chih-Min Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Class-D amplifier;digital-analog conversion;pulse-width modulation (PWM);switching amplifier;timing-skew calibration |
公開日期: | 1-五月-2017 |
摘要: | A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a counter and a delay line for pulse width conversion. The timing skews along the delay line are detected using a zero-crossing detection scheme and corrected in the digital domain. This calibration can operate continuously in the background. A digital CDA prototype was fabricated using a 65-nm CMOS technology. It includes the aforementioned PWM modulator and DPC. It also integrated an open-loop switching driver to deliver the DPC's output to a speaker. This digital CDA consumes 875 mu W under a 1-V supply when the input is zero and no output power is transferred to the external load. It can deliver 13.3 mW to a 32 Omega resistive load in the H-bridge topology with 89% power efficiency. For a 1-kHz sine-wave input, it achieves 95 dBA dynamic range, 93.6 dBA peak SNR, 86.4 dBA peak SNDR, and 0.006% THD at -2-dBFS input level. The core area of the chip is 0.87 x 0.5 mm(2). |
URI: | http://dx.doi.org/10.1109/TCSI.2016.2634016 http://hdl.handle.net/11536/145423 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2016.2634016 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 64 |
起始頁: | 1106 |
結束頁: | 1117 |
顯示於類別: | 期刊論文 |